| Line 10... |
Line 10... |
wbm1_adr_i, wbm1_bte_i, wbm1_cti_i, wbm1_cyc_i, wbm1_dat_i, wbm1_sel_i,
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wbm1_adr_i, wbm1_bte_i, wbm1_cti_i, wbm1_cyc_i, wbm1_dat_i, wbm1_sel_i,
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wbm1_stb_i, wbm1_we_i,
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wbm1_stb_i, wbm1_we_i,
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// Outputs
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// Outputs
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wbm1_ack_o, wbm1_err_o, wbm1_rty_o, wbm1_dat_o,
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wbm1_ack_o, wbm1_err_o, wbm1_rty_o, wbm1_dat_o,
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// Inputs
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wbm2_adr_i, wbm2_bte_i, wbm2_cti_i, wbm2_cyc_i, wbm2_dat_i, wbm2_sel_i,
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wbm2_stb_i, wbm2_we_i,
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// Outputs
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wbm2_ack_o, wbm2_err_o, wbm2_rty_o, wbm2_dat_o,
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// Clock, reset
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// Clock, reset
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wb_clk_i, wb_rst_i
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wb_clk_i, wb_rst_i
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);
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);
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// Bus parameters
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// Bus parameters
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parameter dw = 32;
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parameter dw = 32;
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parameter aw = 32;
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parameter aw = 32;
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// Memory parameters
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// Memory parameters
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parameter mem_span = 32'h0000_0400;
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parameter mem_size_bytes = 32'h0000_0400; // 1KBytes
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parameter adr_width_for_span = 11; //(log2(mem_span));
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parameter mem_adr_width = 10; //(log2(mem_span));
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input [aw-1:0] wbm0_adr_i;
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input [aw-1:0] wbm0_adr_i;
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input [1:0] wbm0_bte_i;
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input [1:0] wbm0_bte_i;
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input [2:0] wbm0_cti_i;
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input [2:0] wbm0_cti_i;
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input wbm0_cyc_i;
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input wbm0_cyc_i;
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| Line 49... |
Line 54... |
output wbm1_ack_o;
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output wbm1_ack_o;
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output wbm1_err_o;
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output wbm1_err_o;
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output wbm1_rty_o;
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output wbm1_rty_o;
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output [dw-1:0] wbm1_dat_o;
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output [dw-1:0] wbm1_dat_o;
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input [aw-1:0] wbm2_adr_i;
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input [1:0] wbm2_bte_i;
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input [2:0] wbm2_cti_i;
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input wbm2_cyc_i;
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input [dw-1:0] wbm2_dat_i;
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input [3:0] wbm2_sel_i;
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input wbm2_stb_i;
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input wbm2_we_i;
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output wbm2_ack_o;
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output wbm2_err_o;
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output wbm2_rty_o;
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output [dw-1:0] wbm2_dat_o;
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input wb_clk_i;
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input wb_clk_i;
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input wb_rst_i;
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input wb_rst_i;
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// Internal wires to actual RAM
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// Internal wires to actual RAM
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wire [aw-1:0] wb_ram_adr_i;
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wire [aw-1:0] wbs_ram_adr_i;
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wire [1:0] wb_ram_bte_i;
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wire [1:0] wbs_ram_bte_i;
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wire [2:0] wb_ram_cti_i;
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wire [2:0] wbs_ram_cti_i;
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wire wb_ram_cyc_i;
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wire wbs_ram_cyc_i;
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wire [dw-1:0] wb_ram_dat_i;
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wire [dw-1:0] wbs_ram_dat_i;
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wire [3:0] wb_ram_sel_i;
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wire [3:0] wbs_ram_sel_i;
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wire wb_ram_stb_i;
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wire wbs_ram_stb_i;
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wire wb_ram_we_i;
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wire wbs_ram_we_i;
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wire wb_ram_ack_o;
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wire wbs_ram_ack_o;
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wire wb_ram_err_o;
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wire wbs_ram_err_o;
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wire wb_ram_rty_o;
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wire wbs_ram_rty_o;
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wire [dw-1:0] wb_ram_dat_o;
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wire [dw-1:0] wbs_ram_dat_o;
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reg [1:0] input_select, last_selected;
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reg [2:0] input_select, last_selected;
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wire arb_for_wbm0, arb_for_wbm1;
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wire arb_for_wbm0, arb_for_wbm1, arb_for_wbm2;
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// Wires allowing selection of new input
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// Wires allowing selection of new input
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assign arb_for_wbm0 = (last_selected[1] | !wbm1_cyc_i) & !(|input_select);
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assign arb_for_wbm0 = (last_selected[1] | last_selected[2] |
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assign arb_for_wbm1 = (last_selected[0] | !wbm0_cyc_i) & !(|input_select);
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!wbm1_cyc_i | !wbm2_cyc_i) & !(|input_select);
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assign arb_for_wbm1 = (last_selected[0] | last_selected[2] |
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!wbm0_cyc_i | !wbm2_cyc_i) & !(|input_select);
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assign arb_for_wbm2 = (last_selected[0] | last_selected[1] |
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!wbm0_cyc_i | !wbm1_cyc_i) & !(|input_select);
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// Master select logic
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// Master select logic
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always @(posedge wb_clk_i)
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always @(posedge wb_clk_i)
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if (wb_rst_i)
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if (wb_rst_i)
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input_select <= 0;
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input_select <= 0;
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else if ((input_select[0] & !wbm0_cyc_i) | (input_select[1] & !wbm1_cyc_i))
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else if ((input_select[0] & !wbm0_cyc_i) | (input_select[1] & !wbm1_cyc_i)
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| (input_select[2] & !wbm2_cyc_i))
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input_select <= 0;
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input_select <= 0;
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else if (!(&input_select) & wbm0_cyc_i & arb_for_wbm0)
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else if (!(&input_select) & wbm0_cyc_i & arb_for_wbm0)
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input_select <= 2'b01;
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input_select <= 3'b001;
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else if (!(&input_select) & wbm1_cyc_i & arb_for_wbm1)
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else if (!(&input_select) & wbm1_cyc_i & arb_for_wbm1)
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input_select <= 2'b10;
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input_select <= 3'b010;
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else if (!(&input_select) & wbm2_cyc_i & arb_for_wbm2)
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input_select <= 3'b100;
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always @(posedge wb_clk_i)
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always @(posedge wb_clk_i)
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if (wb_rst_i)
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if (wb_rst_i)
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last_selected <= 0;
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last_selected <= 0;
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else if (!(&input_select) & wbm0_cyc_i & arb_for_wbm0)
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else if (!(&input_select) & wbm0_cyc_i & arb_for_wbm0)
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last_selected <= 2'b01;
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last_selected <= 3'b001;
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else if (!(&input_select) & wbm1_cyc_i & arb_for_wbm1)
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else if (!(&input_select) & wbm1_cyc_i & arb_for_wbm1)
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last_selected <= 2'b10;
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last_selected <= 3'b010;
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else if (!(&input_select) & wbm2_cyc_i & arb_for_wbm2)
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last_selected <= 3'b100;
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// Mux input signals to RAM (default to wbm0)
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// Mux input signals to RAM (default to wbm0)
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assign wb_ram_adr_i = (input_select[1]) ? wbm1_adr_i :
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assign wbs_ram_adr_i = (input_select[2]) ? wbm2_adr_i :
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(input_select[1]) ? wbm1_adr_i :
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(input_select[0]) ? wbm0_adr_i : 0;
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(input_select[0]) ? wbm0_adr_i : 0;
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assign wb_ram_bte_i = (input_select[1]) ? wbm1_bte_i :
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assign wbs_ram_bte_i = (input_select[2]) ? wbm2_bte_i :
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(input_select[1]) ? wbm1_bte_i :
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(input_select[0]) ? wbm0_bte_i : 0;
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(input_select[0]) ? wbm0_bte_i : 0;
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assign wb_ram_cti_i = (input_select[1]) ? wbm1_cti_i :
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assign wbs_ram_cti_i = (input_select[2]) ? wbm2_cti_i :
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(input_select[1]) ? wbm1_cti_i :
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(input_select[0]) ? wbm0_cti_i : 0;
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(input_select[0]) ? wbm0_cti_i : 0;
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assign wb_ram_cyc_i = (input_select[1]) ? wbm1_cyc_i :
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assign wbs_ram_cyc_i = (input_select[2]) ? wbm2_cyc_i :
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(input_select[1]) ? wbm1_cyc_i :
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(input_select[0]) ? wbm0_cyc_i : 0;
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(input_select[0]) ? wbm0_cyc_i : 0;
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assign wb_ram_dat_i = (input_select[1]) ? wbm1_dat_i :
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assign wbs_ram_dat_i = (input_select[2]) ? wbm2_dat_i :
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(input_select[1]) ? wbm1_dat_i :
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(input_select[0]) ? wbm0_dat_i : 0;
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(input_select[0]) ? wbm0_dat_i : 0;
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assign wb_ram_sel_i = (input_select[1]) ? wbm1_sel_i :
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assign wbs_ram_sel_i = (input_select[2]) ? wbm2_sel_i :
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(input_select[1]) ? wbm1_sel_i :
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(input_select[0]) ? wbm0_sel_i : 0;
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(input_select[0]) ? wbm0_sel_i : 0;
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assign wb_ram_stb_i = (input_select[1]) ? wbm1_stb_i :
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assign wbs_ram_stb_i = (input_select[2]) ? wbm2_stb_i :
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(input_select[1]) ? wbm1_stb_i :
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(input_select[0]) ? wbm0_stb_i : 0;
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(input_select[0]) ? wbm0_stb_i : 0;
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assign wb_ram_we_i = (input_select[1]) ? wbm1_we_i :
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assign wbs_ram_we_i = (input_select[2]) ? wbm2_we_i :
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(input_select[1]) ? wbm1_we_i :
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(input_select[0]) ? wbm0_we_i : 0;
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(input_select[0]) ? wbm0_we_i : 0;
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// Output from RAM, gate the ACK, ERR, RTY signals appropriately
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// Output from RAM, gate the ACK, ERR, RTY signals appropriately
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assign wbm0_dat_o = wb_ram_dat_o;
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assign wbm0_dat_o = wbs_ram_dat_o;
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assign wbm0_ack_o = wb_ram_ack_o & input_select[0];
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assign wbm0_ack_o = wbs_ram_ack_o & input_select[0];
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assign wbm0_err_o = wb_ram_err_o & input_select[0];
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assign wbm0_err_o = wbs_ram_err_o & input_select[0];
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assign wbm0_rty_o = wb_ram_rty_o & input_select[0];
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assign wbm0_rty_o = 0;
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assign wbm1_dat_o = wb_ram_dat_o;
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assign wbm1_dat_o = wbs_ram_dat_o;
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assign wbm1_ack_o = wb_ram_ack_o & input_select[1];
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assign wbm1_ack_o = wbs_ram_ack_o & input_select[1];
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assign wbm1_err_o = wb_ram_err_o & input_select[1];
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assign wbm1_err_o = wbs_ram_err_o & input_select[1];
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assign wbm1_rty_o = wb_ram_rty_o & input_select[1];
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assign wbm1_rty_o = 0;
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assign wbm2_dat_o = wbs_ram_dat_o;
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assign wbm2_ack_o = wbs_ram_ack_o & input_select[2];
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assign wbm2_err_o = wbs_ram_err_o & input_select[2];
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assign wbm2_rty_o = 0;
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ram_wb_b3 ram_wb_b3_0
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ram_wb_b3 ram_wb_b3_0
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(
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(
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// Outputs
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// Outputs
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.wb_ack_o (wb_ram_ack_o),
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.wb_ack_o (wbs_ram_ack_o),
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.wb_err_o (wb_ram_err_o),
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.wb_err_o (wbs_ram_err_o),
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.wb_rty_o (wb_ram_rty_o),
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.wb_rty_o (wbs_ram_rty_o),
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.wb_dat_o (wb_ram_dat_o),
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.wb_dat_o (wbs_ram_dat_o),
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// Inputs
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// Inputs
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.wb_adr_i (wb_ram_adr_i),
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.wb_adr_i (wbs_ram_adr_i),
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.wb_bte_i (wb_ram_bte_i),
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.wb_bte_i (wbs_ram_bte_i),
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.wb_cti_i (wb_ram_cti_i),
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.wb_cti_i (wbs_ram_cti_i),
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.wb_cyc_i (wb_ram_cyc_i),
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.wb_cyc_i (wbs_ram_cyc_i),
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.wb_dat_i (wb_ram_dat_i),
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.wb_dat_i (wbs_ram_dat_i),
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.wb_sel_i (wb_ram_sel_i),
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.wb_sel_i (wbs_ram_sel_i),
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.wb_stb_i (wb_ram_stb_i),
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.wb_stb_i (wbs_ram_stb_i),
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.wb_we_i (wb_ram_we_i),
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.wb_we_i (wbs_ram_we_i),
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.wb_clk_i (wb_clk_i),
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.wb_clk_i (wb_clk_i),
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.wb_rst_i (wb_rst_i));
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.wb_rst_i (wb_rst_i));
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defparam ram_wb_b3_0.aw = aw;
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defparam ram_wb_b3_0.aw = aw;
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defparam ram_wb_b3_0.dw = dw;
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defparam ram_wb_b3_0.dw = dw;
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defparam ram_wb_b3_0.mem_span = mem_span;
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defparam ram_wb_b3_0.mem_size_bytes = mem_size_bytes;
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defparam ram_wb_b3_0.adr_width_for_span = adr_width_for_span;
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defparam ram_wb_b3_0.mem_adr_width = mem_adr_width;
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endmodule // ram_wb
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endmodule // ram_wb
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No newline at end of file
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No newline at end of file
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