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Line 33... |
parameter bytes_per_dw = (dw/8);
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parameter bytes_per_dw = (dw/8);
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parameter adr_width_for_num_word_bytes = 2; //(log2(bytes_per_dw))
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parameter adr_width_for_num_word_bytes = 2; //(log2(bytes_per_dw))
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parameter mem_words = (mem_size_bytes/bytes_per_dw);
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parameter mem_words = (mem_size_bytes/bytes_per_dw);
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// synthesis attribute ram_style of mem is block
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// synthesis attribute ram_style of mem is block
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reg [dw-1:0] mem [ 0 : mem_words-1 ] /* synthesis ram_style = no_rw_check */;
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reg [dw-1:0] mem [ 0 : mem_words-1 ] /* verilator public */ /* synthesis ram_style = no_rw_check */;
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// Register to address internal memory array
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// Register to address internal memory array
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reg [(mem_adr_width-adr_width_for_num_word_bytes)-1:0] adr;
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reg [(mem_adr_width-adr_width_for_num_word_bytes)-1:0] adr;
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wire [31:0] wr_data;
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wire [31:0] wr_data;
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Line 113... |
else if (using_burst_adr)
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else if (using_burst_adr)
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adr <= burst_adr_counter;
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adr <= burst_adr_counter;
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else if (wb_cyc_i & wb_stb_i)
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else if (wb_cyc_i & wb_stb_i)
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adr <= wb_adr_i[mem_adr_width-1:2];
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adr <= wb_adr_i[mem_adr_width-1:2];
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/* Memory initialisation.
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If not Verilator model, always do load, otherwise only load when called
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from SystemC testbench.
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*/
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parameter memory_file = "sram.vmem";
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parameter memory_file = "sram.vmem";
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`ifdef verilator
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task do_readmemh;
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// verilator public
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$readmemh(memory_file, mem);
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endtask // do_readmemh
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`else
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initial
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initial
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begin
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begin
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$readmemh(memory_file, mem);
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$readmemh(memory_file, mem);
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end
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end
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`endif // !`ifdef verilator
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assign wb_rty_o = 0;
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assign wb_rty_o = 0;
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// mux for data to ram, RMW on part sel != 4'hf
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// mux for data to ram, RMW on part sel != 4'hf
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assign wr_data[31:24] = wb_sel_i[3] ? wb_dat_i[31:24] : wb_dat_o[31:24];
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assign wr_data[31:24] = wb_sel_i[3] ? wb_dat_i[31:24] : wb_dat_o[31:24];
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assign wr_data[23:16] = wb_sel_i[2] ? wb_dat_i[23:16] : wb_dat_o[23:16];
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assign wr_data[23:16] = wb_sel_i[2] ? wb_dat_i[23:16] : wb_dat_o[23:16];
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Line 213... |
assign addr_err = wb_cyc_i & wb_stb_i & (|wb_adr_i[aw-1-8:mem_adr_width]);
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assign addr_err = wb_cyc_i & wb_stb_i & (|wb_adr_i[aw-1-8:mem_adr_width]);
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// OR in other errors here...
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// OR in other errors here...
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assign wb_err_o = wb_ack_o & (burst_access_wrong_wb_adr | addr_err);
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assign wb_err_o = wb_ack_o & (burst_access_wrong_wb_adr | addr_err);
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`ifdef verilator
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task do_readmemh;
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// verilator public
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$readmemh(memory_file, mem);
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endtask // do_readmemh
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`else
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initial
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begin
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$readmemh(memory_file, mem);
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end
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`endif // !`ifdef verilator
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//
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//
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// Access functions
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// Access functions
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//
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//
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// Function to access RAM (for use by Verilator).
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// Function to access RAM (for use by Verilator).
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function [31:0] get_mem;
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function [31:0] get_mem32;
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// verilator public
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// verilator public
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input [aw-1:0] addr;
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input [aw-1:0] addr;
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get_mem = mem[addr[mem_adr_width-1:adr_width_for_num_word_bytes]];
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get_mem32 = mem[addr];
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endfunction // get_mem
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endfunction // get_mem32
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// Function to access RAM (for use by Verilator).
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// Function to access RAM (for use by Verilator).
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function [7:0] get_byte;
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function [7:0] get_mem8;
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// verilator public
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// verilator public
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input [aw-1:0] addr;
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input [aw-1:0] addr;
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reg [31:0] temp_word;
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reg [31:0] temp_word;
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begin
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begin
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temp_word = mem[addr[mem_adr_width-1:adr_width_for_num_word_bytes]];
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temp_word = mem[{addr[aw-1:2],2'd0}];
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// Big endian mapping.
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// Big endian mapping.
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get_byte = (addr[1:0]==2'b00) ? temp_word[31:24] :
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get_mem8 = (addr[1:0]==2'b00) ? temp_word[31:24] :
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(addr[1:0]==2'b01) ? temp_word[23:16] :
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(addr[1:0]==2'b01) ? temp_word[23:16] :
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(addr[1:0]==2'b10) ? temp_word[15:8] : temp_word[7:0];
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(addr[1:0]==2'b10) ? temp_word[15:8] : temp_word[7:0];
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end
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end
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endfunction // get_mem
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endfunction // get_mem8
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// Function to write RAM (for use by Verilator).
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// Function to write RAM (for use by Verilator).
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function set_mem;
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function set_mem32;
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// verilator public
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// verilator public
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input [aw-1:0] addr;
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input [aw-1:0] addr;
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input [dw-1:0] data;
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input [dw-1:0] data;
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mem[addr[mem_adr_width-1:adr_width_for_num_word_bytes]] = data;
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mem[addr] = data;
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endfunction // set_mem
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endfunction // set_mem32
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endmodule // ram_wb_b3
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endmodule // ram_wb_b3
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