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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [ram_wb/] [ram_wb_b3.v] - Diff between revs 462 and 546

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Rev 462 Rev 546
Line 60... Line 60...
 
 
   // Logic to detect if there's a burst access going on
   // Logic to detect if there's a burst access going on
   assign wb_b3_trans_start = ((wb_cti_i == 3'b001)|(wb_cti_i == 3'b010)) &
   assign wb_b3_trans_start = ((wb_cti_i == 3'b001)|(wb_cti_i == 3'b010)) &
                              wb_stb_i & !wb_b3_trans;
                              wb_stb_i & !wb_b3_trans;
 
 
   assign  wb_b3_trans_stop = (wb_cti_i == 3'b111) &
   assign  wb_b3_trans_stop = ((wb_cti_i == 3'b111) &
                              wb_stb_i & wb_b3_trans & wb_ack_o;
                              wb_stb_i & wb_b3_trans & wb_ack_o) | wb_err_o;
 
 
   always @(posedge wb_clk_i)
   always @(posedge wb_clk_i)
     if (wb_rst_i)
     if (wb_rst_i)
       wb_b3_trans <= 0;
       wb_b3_trans <= 0;
     else if (wb_b3_trans_start)
     else if (wb_b3_trans_start)
Line 159... Line 159...
     end
     end
 
 
   // Ack Logic
   // Ack Logic
   reg wb_ack_o_r;
   reg wb_ack_o_r;
 
 
   assign wb_ack_o = wb_ack_o_r & wb_stb_i;
   assign wb_ack_o = wb_ack_o_r & wb_stb_i &
 
                     !(burst_access_wrong_wb_adr | addr_err);
 
 
   always @ (posedge wb_clk_i)
   always @ (posedge wb_clk_i)
     if (wb_rst_i)
     if (wb_rst_i)
       wb_ack_o_r <= 1'b0;
       wb_ack_o_r <= 1'b0;
     else if (wb_cyc_i) // We have bus
     else if (wb_cyc_i) // We have bus
Line 211... Line 212...
   // Error when out of bounds of memory - skip top byte of address in case
   // Error when out of bounds of memory - skip top byte of address in case
   // this is mapped somewhere other than 0x00.
   // this is mapped somewhere other than 0x00.
   assign addr_err  = wb_cyc_i & wb_stb_i & (|wb_adr_i[aw-1-8:mem_adr_width]);
   assign addr_err  = wb_cyc_i & wb_stb_i & (|wb_adr_i[aw-1-8:mem_adr_width]);
 
 
   // OR in other errors here...
   // OR in other errors here...
   assign wb_err_o = wb_ack_o & (burst_access_wrong_wb_adr | addr_err);
   assign wb_err_o =  wb_ack_o_r & wb_stb_i &
 
                      (burst_access_wrong_wb_adr | addr_err);
 
 
   //
   //
   // Access functions
   // Access functions
   //
   //
 
 

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