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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [ram_wb/] [ram_wb_b3.v] - Diff between revs 546 and 655

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//`include "synthesis-defines.v"
module ram_wb_b3(
module ram_wb_b3(
                 wb_adr_i, wb_bte_i, wb_cti_i, wb_cyc_i, wb_dat_i, wb_sel_i,
                 wb_adr_i, wb_bte_i, wb_cti_i, wb_cyc_i, wb_dat_i, wb_sel_i,
                 wb_stb_i, wb_we_i,
                 wb_stb_i, wb_we_i,
 
 
                 wb_ack_o, wb_err_o, wb_rty_o, wb_dat_o,
                 wb_ack_o, wb_err_o, wb_rty_o, wb_dat_o,
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   /* Memory initialisation.
   /* Memory initialisation.
    If not Verilator model, always do load, otherwise only load when called
    If not Verilator model, always do load, otherwise only load when called
    from SystemC testbench.
    from SystemC testbench.
    */
    */
 
// synthesis translate_off
   parameter memory_file = "sram.vmem";
   parameter memory_file = "sram.vmem";
 
 
`ifdef verilator
`ifdef verilator
 
 
   task do_readmemh;
   task do_readmemh;
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        $readmemh(memory_file, mem);
        $readmemh(memory_file, mem);
     end
     end
 
 
`endif // !`ifdef verilator
`endif // !`ifdef verilator
 
 
 
//synthesis translate_on
 
 
   assign wb_rty_o = 0;
   assign wb_rty_o = 0;
 
 
   // mux for data to ram, RMW on part sel != 4'hf
   // mux for data to ram, RMW on part sel != 4'hf
   assign wr_data[31:24] = wb_sel_i[3] ? wb_dat_i[31:24] : wb_dat_o[31:24];
   assign wr_data[31:24] = wb_sel_i[3] ? wb_dat_i[31:24] : wb_dat_o[31:24];
   assign wr_data[23:16] = wb_sel_i[2] ? wb_dat_i[23:16] : wb_dat_o[23:16];
   assign wr_data[23:16] = wb_sel_i[2] ? wb_dat_i[23:16] : wb_dat_o[23:16];
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   //
   //
   // Error signal generation
   // Error signal generation
   //
   //
 
 
   // Error when out of bounds of memory - skip top byte of address in case
   // Error when out of bounds of memory - skip top nibble of address in case
   // this is mapped somewhere other than 0x00.
   // this is mapped somewhere other than 0x0.
   assign addr_err  = wb_cyc_i & wb_stb_i & (|wb_adr_i[aw-1-8:mem_adr_width]);
   assign addr_err  = wb_cyc_i & wb_stb_i & (|wb_adr_i[aw-1-4:mem_adr_width]);
 
 
   // OR in other errors here...
   // OR in other errors here...
   assign wb_err_o =  wb_ack_o_r & wb_stb_i &
   assign wb_err_o =  wb_ack_o_r & wb_stb_i &
                      (burst_access_wrong_wb_adr | addr_err);
                      (burst_access_wrong_wb_adr | addr_err);
 
 

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