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//`include "synthesis-defines.v"
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module ram_wb_b3(
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module ram_wb_b3(
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wb_adr_i, wb_bte_i, wb_cti_i, wb_cyc_i, wb_dat_i, wb_sel_i,
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wb_adr_i, wb_bte_i, wb_cti_i, wb_cyc_i, wb_dat_i, wb_sel_i,
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wb_stb_i, wb_we_i,
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wb_stb_i, wb_we_i,
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wb_ack_o, wb_err_o, wb_rty_o, wb_dat_o,
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wb_ack_o, wb_err_o, wb_rty_o, wb_dat_o,
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/* Memory initialisation.
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/* Memory initialisation.
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If not Verilator model, always do load, otherwise only load when called
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If not Verilator model, always do load, otherwise only load when called
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from SystemC testbench.
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from SystemC testbench.
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*/
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*/
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// synthesis translate_off
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parameter memory_file = "sram.vmem";
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parameter memory_file = "sram.vmem";
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`ifdef verilator
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`ifdef verilator
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task do_readmemh;
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task do_readmemh;
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$readmemh(memory_file, mem);
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$readmemh(memory_file, mem);
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end
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end
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`endif // !`ifdef verilator
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`endif // !`ifdef verilator
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//synthesis translate_on
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assign wb_rty_o = 0;
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assign wb_rty_o = 0;
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// mux for data to ram, RMW on part sel != 4'hf
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// mux for data to ram, RMW on part sel != 4'hf
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assign wr_data[31:24] = wb_sel_i[3] ? wb_dat_i[31:24] : wb_dat_o[31:24];
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assign wr_data[31:24] = wb_sel_i[3] ? wb_dat_i[31:24] : wb_dat_o[31:24];
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assign wr_data[23:16] = wb_sel_i[2] ? wb_dat_i[23:16] : wb_dat_o[23:16];
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assign wr_data[23:16] = wb_sel_i[2] ? wb_dat_i[23:16] : wb_dat_o[23:16];
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//
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//
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// Error signal generation
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// Error signal generation
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//
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//
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// Error when out of bounds of memory - skip top byte of address in case
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// Error when out of bounds of memory - skip top nibble of address in case
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// this is mapped somewhere other than 0x00.
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// this is mapped somewhere other than 0x0.
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assign addr_err = wb_cyc_i & wb_stb_i & (|wb_adr_i[aw-1-8:mem_adr_width]);
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assign addr_err = wb_cyc_i & wb_stb_i & (|wb_adr_i[aw-1-4:mem_adr_width]);
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// OR in other errors here...
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// OR in other errors here...
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assign wb_err_o = wb_ack_o_r & wb_stb_i &
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assign wb_err_o = wb_ack_o_r & wb_stb_i &
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(burst_access_wrong_wb_adr | addr_err);
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(burst_access_wrong_wb_adr | addr_err);
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