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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [uart16550/] [raminfr.v] - Diff between revs 6 and 360

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//////////////////////////////////////////////////////////////////////
 
////                                                              ////
 
////  raminfr.v                                                   ////
 
////                                                              ////
 
////                                                              ////
 
////  This file is part of the "UART 16550 compatible" project    ////
 
////  http://www.opencores.org/cores/uart16550/                   ////
 
////                                                              ////
 
////  Documentation related to this project:                      ////
 
////  - http://www.opencores.org/cores/uart16550/                 ////
 
////                                                              ////
 
////  Projects compatibility:                                     ////
 
////  - WISHBONE                                                  ////
 
////  RS232 Protocol                                              ////
 
////  16550D uart (mostly supported)                              ////
 
////                                                              ////
 
////  Overview (main Features):                                   ////
 
////  Inferrable Distributed RAM for FIFOs                        ////
 
////                                                              ////
 
////  Known problems (limits):                                    ////
 
////  None                .                                       ////
 
////                                                              ////
 
////  To Do:                                                      ////
 
////  Nothing so far.                                             ////
 
////                                                              ////
 
////  Author(s):                                                  ////
 
////      - gorban@opencores.org                                  ////
 
////      - Jacob Gorban                                          ////
 
////                                                              ////
 
////  Created:        2002/07/22                                  ////
 
////  Last Updated:   2002/07/22                                  ////
 
////                  (See log for the revision history)          ////
 
////                                                              ////
 
////                                                              ////
 
//////////////////////////////////////////////////////////////////////
 
////                                                              ////
 
//// Copyright (C) 2000, 2001 Authors                             ////
 
////                                                              ////
 
//// This source file may be used and distributed without         ////
 
//// restriction provided that this copyright statement is not    ////
 
//// removed from the file and that any derivative work contains  ////
 
//// the original copyright notice and the associated disclaimer. ////
 
////                                                              ////
 
//// This source file is free software; you can redistribute it   ////
 
//// and/or modify it under the terms of the GNU Lesser General   ////
 
//// Public License as published by the Free Software Foundation; ////
 
//// either version 2.1 of the License, or (at your option) any   ////
 
//// later version.                                               ////
 
////                                                              ////
 
//// This source is distributed in the hope that it will be       ////
 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
 
//// details.                                                     ////
 
////                                                              ////
 
//// You should have received a copy of the GNU Lesser General    ////
 
//// Public License along with this source; if not, download it   ////
 
//// from http://www.opencores.org/lgpl.shtml                     ////
 
////                                                              ////
 
//////////////////////////////////////////////////////////////////////
 
//
 
// CVS Revision History
 
//
 
// $Log: not supported by cvs2svn $
 
// Revision 1.1  2002/07/22 23:02:23  gorban
 
// Bug Fixes:
 
//  * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
 
//   Problem reported by Kenny.Tung.
 
//  * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
 
//
 
// Improvements:
 
//  * Made FIFO's as general inferrable memory where possible.
 
//  So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
 
//  This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
 
//
 
//  * Added optional baudrate output (baud_o).
 
//  This is identical to BAUDOUT* signal on 16550 chip.
 
//  It outputs 16xbit_clock_rate - the divided clock.
 
//  It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
 
//
 
 
 
//Following is the Verilog code for a dual-port RAM with asynchronous read. 
 
module raminfr
 
        (clk, we, a, dpra, di, dpo);
 
 
 
parameter addr_width = 4;
 
parameter data_width = 8;
 
parameter depth = 16;
 
 
 
input clk;
 
input we;
 
input  [addr_width-1:0] a;
 
input  [addr_width-1:0] dpra;
 
input  [data_width-1:0] di;
 
//output [data_width-1:0] spo;   
 
output [data_width-1:0] dpo;
 
reg    [data_width-1:0] ram [depth-1:0];
 
 
 
wire [data_width-1:0] dpo;
 
wire  [data_width-1:0] di;
 
wire  [addr_width-1:0] a;
 
wire  [addr_width-1:0] dpra;
 
 
 
  always @(posedge clk) begin
 
    if (we)
 
      ram[a] <= di;
 
  end
 
//  assign spo = ram[a];   
 
  assign dpo = ram[dpra];
 
endmodule
 
 
 
 
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