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//////////////////////////////////////////////////////////////////////
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//// ////
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//// uart_debug_if.v ////
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//// ////
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//// ////
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//// This file is part of the "UART 16550 compatible" project ////
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//// http://www.opencores.org/cores/uart16550/ ////
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//// ////
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//// Documentation related to this project: ////
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//// - http://www.opencores.org/cores/uart16550/ ////
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//// ////
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//// Projects compatibility: ////
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//// - WISHBONE ////
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//// RS232 Protocol ////
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//// 16550D uart (mostly supported) ////
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//// ////
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//// Overview (main Features): ////
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//// UART core debug interface. ////
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//// ////
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//// Author(s): ////
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//// - gorban@opencores.org ////
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//// - Jacob Gorban ////
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//// ////
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//// Created: 2001/12/02 ////
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//// (See log for the revision history) ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000, 2001 Authors ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2002/07/22 23:02:23 gorban
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// Bug Fixes:
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// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
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// Problem reported by Kenny.Tung.
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// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
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//
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// Improvements:
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// * Made FIFO's as general inferrable memory where possible.
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// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
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// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
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//
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// * Added optional baudrate output (baud_o).
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// This is identical to BAUDOUT* signal on 16550 chip.
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// It outputs 16xbit_clock_rate - the divided clock.
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// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
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//
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// Revision 1.3 2001/12/19 08:40:03 mohor
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// Warnings fixed (unused signals removed).
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//
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// Revision 1.2 2001/12/12 22:17:30 gorban
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// some synthesis bugs fixed
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//
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// Revision 1.1 2001/12/04 21:14:16 gorban
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// committed the debug interface file
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "uart_defines.v"
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module uart_debug_if (/*AUTOARG*/
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// Outputs
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wb_dat32_o,
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// Inputs
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wb_adr_i, ier, iir, fcr, mcr, lcr, msr,
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lsr, rf_count, tf_count, tstate, rstate
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) ;
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input [`UART_ADDR_WIDTH-1:0] wb_adr_i;
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output [31:0] wb_dat32_o;
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input [3:0] ier;
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input [3:0] iir;
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input [1:0] fcr; /// bits 7 and 6 of fcr. Other bits are ignored
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input [4:0] mcr;
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input [7:0] lcr;
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input [7:0] msr;
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input [7:0] lsr;
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input [`UART_FIFO_COUNTER_W-1:0] rf_count;
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input [`UART_FIFO_COUNTER_W-1:0] tf_count;
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input [2:0] tstate;
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input [3:0] rstate;
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wire [`UART_ADDR_WIDTH-1:0] wb_adr_i;
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reg [31:0] wb_dat32_o;
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always @(/*AUTOSENSE*/fcr or ier or iir or lcr or lsr or mcr or msr
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or rf_count or rstate or tf_count or tstate or wb_adr_i)
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case (wb_adr_i)
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// 8 + 8 + 4 + 4 + 8
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5'b01000: wb_dat32_o = {msr,lcr,iir,ier,lsr};
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// 5 + 2 + 5 + 4 + 5 + 3
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5'b01100: wb_dat32_o = {8'b0, fcr,mcr, rf_count, rstate, tf_count, tstate};
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default: wb_dat32_o = 0;
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endcase // case(wb_adr_i)
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endmodule // uart_debug_if
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