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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [uart16550/] [uart_transmitter.v] - Diff between revs 360 and 363

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Rev 360 Rev 363
Line 267... Line 267...
                                begin
                                begin
                                        counter <=  0;
                                        counter <=  0;
                                        tstate <=  s_send_byte;
                                        tstate <=  s_send_byte;
                                end
                                end
                                else
                                else
                                        counter <=  counter - 1'b1;
                                        counter <=  counter - 5'd1;
                                stx_o_tmp <=  1'b0;
                                stx_o_tmp <=  1'b0;
                        end
                        end
        s_send_byte :   begin
        s_send_byte :   begin
                                if (~|counter)
                                if (~|counter)
                                        counter <=  5'b01111;
                                        counter <=  5'b01111;
                                else
                                else
                                if (counter == 5'b00001)
                                if (counter == 5'b00001)
                                begin
                                begin
                                        if (bit_counter > 3'b0)
                                        if (bit_counter > 3'b0)
                                        begin
                                        begin
                                                bit_counter <=  bit_counter - 1'b1;
                                                bit_counter <=  bit_counter - 3'd1;
                                                {shift_out[5:0],bit_out  } <=  {shift_out[6:1], shift_out[0]};
                                                {shift_out[5:0],bit_out  } <=  {shift_out[6:1], shift_out[0]};
                                                tstate <=  s_send_byte;
                                                tstate <=  s_send_byte;
                                        end
                                        end
                                        else   // end of byte
                                        else   // end of byte
                                        if (~lcr[`UART_LC_PE])
                                        if (~lcr[`UART_LC_PE])
Line 300... Line 300...
                                                tstate <=  s_send_parity;
                                                tstate <=  s_send_parity;
                                        end
                                        end
                                        counter <=  0;
                                        counter <=  0;
                                end
                                end
                                else
                                else
                                        counter <=  counter - 1'b1;
                                        counter <=  counter - 5'd1;
                                stx_o_tmp <=  bit_out; // set output pin
                                stx_o_tmp <=  bit_out; // set output pin
                        end
                        end
        s_send_parity : begin
        s_send_parity : begin
                                if (~|counter)
                                if (~|counter)
                                        counter <=  5'b01111;
                                        counter <=  5'b01111;
                                else
                                else
                                if (counter == 5'b00001)
                                if (counter == 5'b00001)
                                begin
                                begin
                                        counter <=  4'b0;
                                        counter <=  5'd0;
                                        tstate <=  s_send_stop;
                                        tstate <=  s_send_stop;
                                end
                                end
                                else
                                else
                                        counter <=  counter - 1'b1;
                                        counter <=  counter - 5'd1;
                                stx_o_tmp <=  bit_out;
                                stx_o_tmp <=  bit_out;
                        end
                        end
        s_send_stop :  begin
        s_send_stop :  begin
                                if (~|counter)
                                if (~|counter)
                                  begin
                                  begin
                                                casex ({lcr[`UART_LC_SB],lcr[`UART_LC_BITS]})
                                                casez ({lcr[`UART_LC_SB],lcr[`UART_LC_BITS]})
                                                3'b0xx:   counter <=  5'b01101;     // 1 stop bit ok igor
                                                3'b0??:   counter <=  5'b01101;     // 1 stop bit ok igor
                                                3'b100:   counter <=  5'b10101;     // 1.5 stop bit
                                                3'b100:   counter <=  5'b10101;     // 1.5 stop bit
                                                default:          counter <=  5'b11101;     // 2 stop bits
                                                default:          counter <=  5'b11101;     // 2 stop bits
                                                endcase
                                                endcase
                                        end
                                        end
                                else
                                else
Line 332... Line 332...
                                begin
                                begin
                                        counter <=  0;
                                        counter <=  0;
                                        tstate <=  s_idle;
                                        tstate <=  s_idle;
                                end
                                end
                                else
                                else
                                        counter <=  counter - 1'b1;
                                        counter <=  counter - 5'd1;
                                stx_o_tmp <=  1'b1;
                                stx_o_tmp <=  1'b1;
                        end
                        end
 
 
                default : // should never get here
                default : // should never get here
                        tstate <=  s_idle;
                        tstate <=  s_idle;

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