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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [wb_ram_b3/] [wb_ram_b3.v] - Diff between revs 362 and 363

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Rev 362 Rev 363
Line 13... Line 13...
 
 
   // Memory parameters
   // Memory parameters
   parameter dw = 32;
   parameter dw = 32;
 
 
   // 32MB memory by default
   // 32MB memory by default
   parameter aw = 25;
   parameter aw = 23;
   parameter mem_size  = 8388608;
   parameter mem_size  = 8388608;
 
 
   input [aw-1:0]        wb_adr_i;
   input [aw-1:0]        wb_adr_i;
   input [1:0]           wb_bte_i;
   input [1:0]           wb_bte_i;
   input [2:0]           wb_cti_i;
   input [2:0]           wb_cti_i;
Line 38... Line 38...
 
 
   // synthesis attribute ram_style of mem is block
   // synthesis attribute ram_style of mem is block
   reg [dw-1:0]  mem [ 0 : mem_size-1 ]  /* verilator public */ /* synthesis ram_style = no_rw_check */;
   reg [dw-1:0]  mem [ 0 : mem_size-1 ]  /* verilator public */ /* synthesis ram_style = no_rw_check */;
 
 
   //reg [aw-1:2] wb_adr_i_r;
   //reg [aw-1:2] wb_adr_i_r;
   reg [(aw-2)-1:0] adr;
   reg [aw-1:0] adr;
 
 
   wire [31:0]                      wr_data;
   wire [31:0]                      wr_data;
 
 
   // Register to indicate if the cycle is a Wishbone B3-registered feedback 
   // Register to indicate if the cycle is a Wishbone B3-registered feedback 
   // type access
   // type access
   reg                             wb_b3_trans;
   reg                             wb_b3_trans;
   wire                            wb_b3_trans_start, wb_b3_trans_stop;
   wire                            wb_b3_trans_start, wb_b3_trans_stop;
 
 
   // Register to use for counting the addresses when doing burst accesses
   // Register to use for counting the addresses when doing burst accesses
   reg [aw-1-2:0]  burst_adr_counter;
   reg [aw-1:0]  burst_adr_counter;
   reg [2:0]                        wb_cti_i_r;
   reg [2:0]                        wb_cti_i_r;
   reg [1:0]                        wb_bte_i_r;
   reg [1:0]                        wb_bte_i_r;
   wire                            using_burst_adr;
   wire                            using_burst_adr;
   wire                            burst_access_wrong_wb_adr;
   wire                            burst_access_wrong_wb_adr;
 
 
Line 76... Line 76...
   // Burst address generation logic
   // Burst address generation logic
   always @*
   always @*
     if (wb_rst_i)
     if (wb_rst_i)
       burst_adr_counter = 0;
       burst_adr_counter = 0;
     else if (wb_b3_trans_start)
     else if (wb_b3_trans_start)
       burst_adr_counter = wb_adr_i[aw-1:2];
       burst_adr_counter = {2'b00,wb_adr_i[aw-1:2]};
     else if ((wb_cti_i_r == 3'b010) & wb_ack_o & wb_b3_trans)
     else if ((wb_cti_i_r == 3'b010) & wb_ack_o & wb_b3_trans)
       // Incrementing burst
       // Incrementing burst
       begin
       begin
          if (wb_bte_i_r == 2'b00) // Linear burst
          if (wb_bte_i_r == 2'b00) // Linear burst
            burst_adr_counter = adr + 1;
            burst_adr_counter = adr + 1;
Line 102... Line 102...
   always @(posedge wb_clk_i)
   always @(posedge wb_clk_i)
     wb_cti_i_r <= wb_cti_i;
     wb_cti_i_r <= wb_cti_i;
 
 
   assign using_burst_adr = wb_b3_trans;
   assign using_burst_adr = wb_b3_trans;
 
 
   assign burst_access_wrong_wb_adr = (using_burst_adr & (adr != wb_adr_i[aw-1:2]));
   assign burst_access_wrong_wb_adr = (using_burst_adr & (adr != {2'b00,wb_adr_i[aw-1:2]}));
 
 
   // Address registering logic
   // Address registering logic
   always@(posedge wb_clk_i)
   always@(posedge wb_clk_i)
     if(wb_rst_i)
     if(wb_rst_i)
       adr <= 0;
       adr <= 0;
     else if (using_burst_adr)
     else if (using_burst_adr)
       adr <= burst_adr_counter;
       adr <= burst_adr_counter;
     else if (wb_cyc_i & wb_stb_i)
     else if (wb_cyc_i & wb_stb_i)
       adr <= wb_adr_i[aw-1:2];
       adr <= {2'b00,wb_adr_i[aw-1:2]};
 
 
   parameter memory_file = "sram.vmem";
   parameter memory_file = "sram.vmem";
 
 
 
 
`ifdef verilator
`ifdef verilator

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