| Line 13... |
Line 13... |
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// Memory parameters
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// Memory parameters
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parameter dw = 32;
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parameter dw = 32;
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// 32MB memory by default
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// 32MB memory by default
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parameter aw = 25;
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parameter aw = 23;
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parameter mem_size = 8388608;
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parameter mem_size = 8388608;
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input [aw-1:0] wb_adr_i;
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input [aw-1:0] wb_adr_i;
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input [1:0] wb_bte_i;
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input [1:0] wb_bte_i;
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input [2:0] wb_cti_i;
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input [2:0] wb_cti_i;
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| Line 38... |
Line 38... |
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// synthesis attribute ram_style of mem is block
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// synthesis attribute ram_style of mem is block
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reg [dw-1:0] mem [ 0 : mem_size-1 ] /* verilator public */ /* synthesis ram_style = no_rw_check */;
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reg [dw-1:0] mem [ 0 : mem_size-1 ] /* verilator public */ /* synthesis ram_style = no_rw_check */;
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//reg [aw-1:2] wb_adr_i_r;
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//reg [aw-1:2] wb_adr_i_r;
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reg [(aw-2)-1:0] adr;
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reg [aw-1:0] adr;
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wire [31:0] wr_data;
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wire [31:0] wr_data;
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// Register to indicate if the cycle is a Wishbone B3-registered feedback
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// Register to indicate if the cycle is a Wishbone B3-registered feedback
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// type access
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// type access
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reg wb_b3_trans;
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reg wb_b3_trans;
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wire wb_b3_trans_start, wb_b3_trans_stop;
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wire wb_b3_trans_start, wb_b3_trans_stop;
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// Register to use for counting the addresses when doing burst accesses
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// Register to use for counting the addresses when doing burst accesses
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reg [aw-1-2:0] burst_adr_counter;
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reg [aw-1:0] burst_adr_counter;
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reg [2:0] wb_cti_i_r;
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reg [2:0] wb_cti_i_r;
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reg [1:0] wb_bte_i_r;
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reg [1:0] wb_bte_i_r;
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wire using_burst_adr;
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wire using_burst_adr;
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wire burst_access_wrong_wb_adr;
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wire burst_access_wrong_wb_adr;
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| Line 76... |
Line 76... |
// Burst address generation logic
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// Burst address generation logic
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always @*
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always @*
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if (wb_rst_i)
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if (wb_rst_i)
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burst_adr_counter = 0;
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burst_adr_counter = 0;
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else if (wb_b3_trans_start)
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else if (wb_b3_trans_start)
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burst_adr_counter = wb_adr_i[aw-1:2];
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burst_adr_counter = {2'b00,wb_adr_i[aw-1:2]};
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else if ((wb_cti_i_r == 3'b010) & wb_ack_o & wb_b3_trans)
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else if ((wb_cti_i_r == 3'b010) & wb_ack_o & wb_b3_trans)
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// Incrementing burst
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// Incrementing burst
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begin
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begin
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if (wb_bte_i_r == 2'b00) // Linear burst
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if (wb_bte_i_r == 2'b00) // Linear burst
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burst_adr_counter = adr + 1;
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burst_adr_counter = adr + 1;
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| Line 102... |
Line 102... |
always @(posedge wb_clk_i)
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always @(posedge wb_clk_i)
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wb_cti_i_r <= wb_cti_i;
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wb_cti_i_r <= wb_cti_i;
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assign using_burst_adr = wb_b3_trans;
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assign using_burst_adr = wb_b3_trans;
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assign burst_access_wrong_wb_adr = (using_burst_adr & (adr != wb_adr_i[aw-1:2]));
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assign burst_access_wrong_wb_adr = (using_burst_adr & (adr != {2'b00,wb_adr_i[aw-1:2]}));
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// Address registering logic
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// Address registering logic
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always@(posedge wb_clk_i)
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always@(posedge wb_clk_i)
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if(wb_rst_i)
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if(wb_rst_i)
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adr <= 0;
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adr <= 0;
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else if (using_burst_adr)
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else if (using_burst_adr)
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adr <= burst_adr_counter;
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adr <= burst_adr_counter;
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else if (wb_cyc_i & wb_stb_i)
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else if (wb_cyc_i & wb_stb_i)
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adr <= wb_adr_i[aw-1:2];
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adr <= {2'b00,wb_adr_i[aw-1:2]};
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parameter memory_file = "sram.vmem";
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parameter memory_file = "sram.vmem";
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`ifdef verilator
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`ifdef verilator
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