| Line 18... |
Line 18... |
# Suppressed warnings - 8598: Non-positive replication multiplier inside concat. Replication will be ignored
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# Suppressed warnings - 8598: Non-positive replication multiplier inside concat. Replication will be ignored
|
VSIM_ARGS= -suppress 7 -suppress 3009 -suppress 8598 -c $(QUIET) -do "set StdArithNoWarnings 1; run -all; exit"
|
VSIM_ARGS= -suppress 7 -suppress 3009 -suppress 8598 -c $(QUIET) -do "set StdArithNoWarnings 1; run -all; exit"
|
|
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# VPI debugging interface set up
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# VPI debugging interface set up
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VPI_SRC_C_DIR=$(COMMON_BENCH_VERILOG_DIR)/vpi/c
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VPI_SRC_C_DIR=$(COMMON_BENCH_VERILOG_DIR)/vpi/c
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VPI_SRC_VERILOG_DIR=vpi/verilog
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VPI_SRCS=$(shell ls $(VPI_SRC_C_DIR)/*.[ch])
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VPI_SRCS=$(shell ls $(VPI_SRC_C_DIR)/*.[ch])
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|
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# Modelsim VPI compile variables
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# Modelsim VPI compile variables
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MODELTECH_VPILIB=msim_jp_vpi.sl
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MODELTECH_VPILIB=msim_jp_vpi.sl
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|
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| Line 95... |
Line 94... |
|
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# Compile DUT into "work" library
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# Compile DUT into "work" library
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work: modelsim_dut.scr
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work: modelsim_dut.scr
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$(Q)if [ ! -e $@ ]; then vlib $@; fi
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$(Q)if [ ! -e $@ ]; then vlib $@; fi
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$(Q)echo; echo "\t### Compiling Verilog design library ###"; echo
|
$(Q)echo; echo "\t### Compiling Verilog design library ###"; echo
|
$(Q)vlog $(QUIET) -f $< $(DUT_TOP)
|
$(Q)vlog $(QUIET) -f $< $(DUT_TOP_FILE)
|
|
$(Q)if [ "$(RTL_VHDL_SRC)" != "" ]; then \
|
|
echo; echo "\t### Compiling VHDL design library ###"; \
|
|
echo; \
|
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vcom -93 $(QUIET) $(RTL_VHDL_SRC); \
|
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fi
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|
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#
|
#
|
# Run rule
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# Run rule, one for each vendor
|
#
|
#
|
|
|
.PHONY : $(MODELSIM)
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.PHONY : $(MODELSIM)
|
ifeq ($(FPGA_VENDOR), actel)
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ifeq ($(FPGA_VENDOR), actel)
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$(MODELSIM): modelsim_bench.scr $(TEST_DEFINES_VLG) $(BACKEND_LIB) $(VPI_LIBS) work
|
$(MODELSIM): modelsim_bench.scr $(TEST_DEFINES_VLG) $(BACKEND_LIB) $(VPI_LIBS) work
|
$(Q)echo; echo "\t### Compiling testbench ###"; echo
|
$(Q)echo; echo "\t### Compiling testbench ###"; echo
|
$(Q)vlog $(QUIET) -nologo -incr $(BENCH_TOP) -f $<
|
$(Q)vlog $(QUIET) -nologo -incr $(BENCH_TOP_FILE) -f $<
|
$(Q)vopt $(QUIET) $(RTL_TESTBENCH_TOP) $(VOPT_ARGS) -L $(BACKEND_LIB) \
|
$(Q)vopt $(QUIET) $(RTL_TESTBENCH_TOP_NAME) $(VOPT_ARGS) \
|
-o tb
|
-L $(BACKEND_LIB) -o tb
|
$(Q)echo; echo "\t### Launching simulation ###"; echo
|
$(Q)echo; echo "\t### Launching simulation ###"; echo
|
$(Q)vsim $(VSIM_ARGS) tb
|
$(Q)vsim $(VSIM_ARGS) tb
|
endif
|
endif
|
|
|
ifeq ($(FPGA_VENDOR), xilinx)
|
ifeq ($(FPGA_VENDOR), xilinx)
|
$(MODELSIM): modelsim_bench.scr $(TEST_DEFINES_VLG) $(VPI_LIBS) work
|
$(MODELSIM): modelsim_bench.scr $(TEST_DEFINES_VLG) $(VPI_LIBS) work
|
$(Q)echo; echo "\t### Compiling Xilinx support libs, user design & testbench ###"; echo
|
$(Q)echo; echo "\t### Compiling Xilinx support libs, user design & testbench ###"; echo
|
$(Q)vlog $(QUIET) -nologo -incr $(BENCH_TOP) -f $<
|
$(Q)vlog $(QUIET) -nologo -incr $(BENCH_TOP_FILE) -f $<
|
$(Q)vopt $(QUIET) glbl $(RTL_TESTBENCH_TOP) $(VOPT_ARGS) -o tb
|
$(Q)vopt $(QUIET) glbl $(RTL_TESTBENCH_TOP_NAME) $(VOPT_ARGS) -o tb
|
$(Q)echo; echo "\t### Launching simulation ###"; echo
|
$(Q)echo; echo "\t### Launching simulation ###"; echo
|
$(Q)vsim $(VSIM_ARGS) tb
|
$(Q)vsim $(VSIM_ARGS) tb
|
endif
|
endif
|
|
|
|
ifeq ($(FPGA_VENDOR), altera)
|
|
$(MODELSIM): modelsim_bench.scr $(TEST_DEFINES_VLG) $(BACKEND_LIB) $(VPI_LIBS) work
|
|
$(Q)echo; echo "\t### Compiling testbench ###"; echo
|
|
$(Q)vlog $(QUIET) -nologo -incr $(BENCH_TOP_FILE) -f $<
|
|
$(Q)vopt $(QUIET) $(RTL_TESTBENCH_TOP_NAME) $(VOPT_ARGS) \
|
|
-L $(BACKEND_LIB) -o tb
|
|
$(Q)echo; echo "\t### Launching simulation ###"; echo
|
|
$(Q)vsim $(VSIM_ARGS) tb
|
|
endif
|
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