| Line 3... |
Line 3... |
#
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#
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# Modelsim-specific settings
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# Modelsim-specific settings
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#
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#
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VOPT_ARGS+=$(QUIET) -suppress 2241
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VOPT_ARGS+=$(QUIET) -suppress 2241
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# If certain versions of modelsim don't have the vopt executable, define
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# MGC_NO_VOPT=1 when running to skip use of the vopt executable
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ifeq ($(MGC_NO_VOPT), 1)
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MGC_VOPT_EXE= \# skipped: vopt
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# When no vopt stage, actual vsim target changes, and extra options
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# must be passed depending on FPGA tech
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ifeq ($(FPGA_VENDOR), xilinx)
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MGC_VSIM_TGT=orpsoc_testbench glbl
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else
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MGC_VSIM_TGT=orpsoc_testbench -L $(BACKEND_LIB)
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endif
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else
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MGC_VOPT_EXE= vopt
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MGC_VSIM_TGT=tb
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endif
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# If VCD dump is desired, tell Modelsim not to optimise
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# If VCD dump is desired, tell Modelsim not to optimise
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# away everything.
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# away everything.
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ifeq ($(VCD), 1)
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ifeq ($(VCD), 1)
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#VOPT_ARGS=-voptargs="+acc=rnp"
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#VOPT_ARGS=-voptargs="+acc=rnp"
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VOPT_ARGS+=+acc=rnpqv
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VOPT_ARGS+=+acc=rnpqv
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| Line 110... |
Line 129... |
.PHONY : $(MODELSIM)
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.PHONY : $(MODELSIM)
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ifeq ($(FPGA_VENDOR), actel)
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ifeq ($(FPGA_VENDOR), actel)
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$(MODELSIM): modelsim_bench.scr $(TEST_DEFINES_VLG) $(BACKEND_LIB) $(VPI_LIBS) work
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$(MODELSIM): modelsim_bench.scr $(TEST_DEFINES_VLG) $(BACKEND_LIB) $(VPI_LIBS) work
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$(Q)echo; echo "\t### Compiling testbench ###"; echo
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$(Q)echo; echo "\t### Compiling testbench ###"; echo
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$(Q)vlog $(QUIET) -nologo -incr $(BENCH_TOP_FILE) -f $<
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$(Q)vlog $(QUIET) -nologo -incr $(BENCH_TOP_FILE) -f $<
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$(Q)vopt $(QUIET) $(RTL_TESTBENCH_TOP_NAME) $(VOPT_ARGS) \
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$(Q)$(MGC_VOPT_EXE) $(QUIET) $(RTL_TESTBENCH_TOP_NAME) $(VOPT_ARGS) -L $(BACKEND_LIB) -o tb
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-L $(BACKEND_LIB) -o tb
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$(Q)echo; echo "\t### Launching simulation ###"; echo
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$(Q)echo; echo "\t### Launching simulation ###"; echo
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$(Q)vsim $(VSIM_ARGS) tb
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$(Q)vsim $(VSIM_ARGS) $(MGC_VSIM_TGT)
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endif
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endif
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ifeq ($(FPGA_VENDOR), xilinx)
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ifeq ($(FPGA_VENDOR), xilinx)
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$(MODELSIM): modelsim_bench.scr $(TEST_DEFINES_VLG) $(VPI_LIBS) work
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$(MODELSIM): modelsim_bench.scr $(TEST_DEFINES_VLG) $(VPI_LIBS) work
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$(Q)echo; echo "\t### Compiling Xilinx support libs, user design & testbench ###"; echo
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$(Q)echo; echo "\t### Compiling Xilinx support libs, user design & testbench ###"; echo
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ifeq ($(DO_XILINX_COMPXLIB), 1)
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ifeq ($(DO_XILINX_COMPXLIB), 1)
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$(Q)$(TECHNOLOGY_BACKEND_BIN_DIR)/compxlib $(XLIB_ARGS)
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$(Q)$(TECHNOLOGY_BACKEND_BIN_DIR)/compxlib $(XLIB_ARGS)
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endif
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endif
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$(Q)vlog $(QUIET) -nologo -incr $(BENCH_TOP_FILE) -f $<
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$(Q)vlog $(QUIET) -nologo -incr $(BENCH_TOP_FILE) -f $<
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$(Q)vopt $(QUIET) glbl $(RTL_TESTBENCH_TOP_NAME) $(VOPT_ARGS) -o tb
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$(Q)$(MGC_VOPT_EXE) $(QUIET) glbl $(RTL_TESTBENCH_TOP_NAME) $(VOPT_ARGS) -o tb
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$(Q)echo; echo "\t### Launching simulation ###"; echo
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$(Q)echo; echo "\t### Launching simulation ###"; echo
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$(Q)vsim $(VSIM_ARGS) tb
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$(Q)vsim $(VSIM_ARGS) $(MGC_VSIM_TGT)
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endif
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endif
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|
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ifeq ($(FPGA_VENDOR), altera)
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ifeq ($(FPGA_VENDOR), altera)
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$(MODELSIM): modelsim_bench.scr $(TEST_DEFINES_VLG) $(BACKEND_LIB) $(VPI_LIBS) work
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$(MODELSIM): modelsim_bench.scr $(TEST_DEFINES_VLG) $(BACKEND_LIB) $(VPI_LIBS) work
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$(Q)echo; echo "\t### Compiling testbench ###"; echo
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$(Q)echo; echo "\t### Compiling testbench ###"; echo
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$(Q)vlog $(QUIET) -nologo -incr $(BENCH_TOP_FILE) -f $<
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$(Q)vlog $(QUIET) -nologo -incr $(BENCH_TOP_FILE) -f $<
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$(Q)vopt $(QUIET) $(RTL_TESTBENCH_TOP_NAME) $(VOPT_ARGS) \
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$(Q)$(MGC_VOPT_EXE) $(QUIET) $(RTL_TESTBENCH_TOP_NAME) $(VOPT_ARGS) -L $(BACKEND_LIB) -o tb
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-L $(BACKEND_LIB) -o tb
|
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$(Q)echo; echo "\t### Launching simulation ###"; echo
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$(Q)echo; echo "\t### Launching simulation ###"; echo
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$(Q)vsim $(VSIM_ARGS) tb
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$(Q)vsim $(VSIM_ARGS) $(MGC_VSIM_TGT)
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endif
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endif
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