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[/] [openrisc/] [trunk/] [orpsocv2/] [scripts/] [make/] [Makefile-board-modelsim.inc] - Diff between revs 562 and 651

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Line 3... Line 3...
#
#
# Modelsim-specific settings
# Modelsim-specific settings
#
#
VOPT_ARGS+=$(QUIET) -suppress 2241
VOPT_ARGS+=$(QUIET) -suppress 2241
 
 
 
# If certain versions of modelsim don't have the vopt executable, define
 
# MGC_NO_VOPT=1 when running to skip use of the vopt executable
 
ifeq ($(MGC_NO_VOPT), 1)
 
MGC_VOPT_EXE= \# skipped: vopt
 
 
 
# When no vopt stage, actual vsim target changes, and extra options
 
# must be passed depending on FPGA tech
 
ifeq ($(FPGA_VENDOR), xilinx)
 
MGC_VSIM_TGT=orpsoc_testbench glbl
 
else
 
MGC_VSIM_TGT=orpsoc_testbench -L $(BACKEND_LIB)
 
endif
 
 
 
else
 
MGC_VOPT_EXE= vopt
 
MGC_VSIM_TGT=tb
 
endif
 
 
 
 
# If VCD dump is desired, tell Modelsim not to optimise
# If VCD dump is desired, tell Modelsim not to optimise
# away everything.
# away everything.
ifeq ($(VCD), 1)
ifeq ($(VCD), 1)
#VOPT_ARGS=-voptargs="+acc=rnp"
#VOPT_ARGS=-voptargs="+acc=rnp"
VOPT_ARGS+=+acc=rnpqv
VOPT_ARGS+=+acc=rnpqv
Line 110... Line 129...
.PHONY : $(MODELSIM)
.PHONY : $(MODELSIM)
ifeq ($(FPGA_VENDOR), actel)
ifeq ($(FPGA_VENDOR), actel)
$(MODELSIM): modelsim_bench.scr $(TEST_DEFINES_VLG) $(BACKEND_LIB) $(VPI_LIBS) work
$(MODELSIM): modelsim_bench.scr $(TEST_DEFINES_VLG) $(BACKEND_LIB) $(VPI_LIBS) work
        $(Q)echo; echo "\t### Compiling testbench ###"; echo
        $(Q)echo; echo "\t### Compiling testbench ###"; echo
        $(Q)vlog $(QUIET) -nologo -incr $(BENCH_TOP_FILE) -f $<
        $(Q)vlog $(QUIET) -nologo -incr $(BENCH_TOP_FILE) -f $<
        $(Q)vopt $(QUIET) $(RTL_TESTBENCH_TOP_NAME) $(VOPT_ARGS) \
        $(Q)$(MGC_VOPT_EXE) $(QUIET) $(RTL_TESTBENCH_TOP_NAME) $(VOPT_ARGS) -L $(BACKEND_LIB) -o tb
        -L $(BACKEND_LIB) -o tb
 
        $(Q)echo; echo "\t### Launching simulation ###"; echo
        $(Q)echo; echo "\t### Launching simulation ###"; echo
        $(Q)vsim $(VSIM_ARGS) tb
        $(Q)vsim $(VSIM_ARGS) $(MGC_VSIM_TGT)
endif
endif
 
 
ifeq ($(FPGA_VENDOR), xilinx)
ifeq ($(FPGA_VENDOR), xilinx)
$(MODELSIM): modelsim_bench.scr $(TEST_DEFINES_VLG) $(VPI_LIBS) work
$(MODELSIM): modelsim_bench.scr $(TEST_DEFINES_VLG) $(VPI_LIBS) work
        $(Q)echo; echo "\t### Compiling Xilinx support libs, user design & testbench ###"; echo
        $(Q)echo; echo "\t### Compiling Xilinx support libs, user design & testbench ###"; echo
ifeq ($(DO_XILINX_COMPXLIB), 1)
ifeq ($(DO_XILINX_COMPXLIB), 1)
        $(Q)$(TECHNOLOGY_BACKEND_BIN_DIR)/compxlib $(XLIB_ARGS)
        $(Q)$(TECHNOLOGY_BACKEND_BIN_DIR)/compxlib $(XLIB_ARGS)
endif
endif
        $(Q)vlog $(QUIET) -nologo -incr $(BENCH_TOP_FILE) -f $<
        $(Q)vlog $(QUIET) -nologo -incr $(BENCH_TOP_FILE) -f $<
        $(Q)vopt $(QUIET) glbl $(RTL_TESTBENCH_TOP_NAME) $(VOPT_ARGS) -o tb
        $(Q)$(MGC_VOPT_EXE) $(QUIET) glbl $(RTL_TESTBENCH_TOP_NAME) $(VOPT_ARGS) -o tb
        $(Q)echo; echo "\t### Launching simulation ###"; echo
        $(Q)echo; echo "\t### Launching simulation ###"; echo
        $(Q)vsim $(VSIM_ARGS) tb
        $(Q)vsim $(VSIM_ARGS) $(MGC_VSIM_TGT)
endif
endif
 
 
ifeq ($(FPGA_VENDOR), altera)
ifeq ($(FPGA_VENDOR), altera)
$(MODELSIM): modelsim_bench.scr $(TEST_DEFINES_VLG) $(BACKEND_LIB) $(VPI_LIBS) work
$(MODELSIM): modelsim_bench.scr $(TEST_DEFINES_VLG) $(BACKEND_LIB) $(VPI_LIBS) work
        $(Q)echo; echo "\t### Compiling testbench ###"; echo
        $(Q)echo; echo "\t### Compiling testbench ###"; echo
        $(Q)vlog $(QUIET) -nologo -incr $(BENCH_TOP_FILE) -f $<
        $(Q)vlog $(QUIET) -nologo -incr $(BENCH_TOP_FILE) -f $<
        $(Q)vopt $(QUIET) $(RTL_TESTBENCH_TOP_NAME) $(VOPT_ARGS) \
        $(Q)$(MGC_VOPT_EXE) $(QUIET) $(RTL_TESTBENCH_TOP_NAME) $(VOPT_ARGS) -L $(BACKEND_LIB) -o tb
        -L $(BACKEND_LIB) -o tb
 
        $(Q)echo; echo "\t### Launching simulation ###"; echo
        $(Q)echo; echo "\t### Launching simulation ###"; echo
        $(Q)vsim $(VSIM_ARGS) tb
        $(Q)vsim $(VSIM_ARGS) $(MGC_VSIM_TGT)
endif
endif
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