| Line 13... |
Line 13... |
# When no vopt stage, actual vsim target changes, and extra options
|
# When no vopt stage, actual vsim target changes, and extra options
|
# must be passed depending on FPGA tech
|
# must be passed depending on FPGA tech
|
ifeq ($(FPGA_VENDOR), xilinx)
|
ifeq ($(FPGA_VENDOR), xilinx)
|
MGC_VSIM_TGT=orpsoc_testbench glbl
|
MGC_VSIM_TGT=orpsoc_testbench glbl
|
else
|
else
|
MGC_VSIM_TGT=orpsoc_testbench -L $(BACKEND_LIB)
|
MGC_VSIM_TGT=orpsoc_testbench
|
endif
|
endif
|
|
|
else
|
else
|
MGC_VOPT_EXE= vopt
|
MGC_VOPT_EXE= vopt
|
MGC_VSIM_TGT=tb
|
MGC_VSIM_TGT=tb
|
| Line 33... |
Line 33... |
|
|
# VSIM commands
|
# VSIM commands
|
# Suppressed warnings - 3009: Failed to open $readmemh() file
|
# Suppressed warnings - 3009: Failed to open $readmemh() file
|
# Suppressed warnings - 3009: Module 'blah' does not have a `timescale directive in effect, but previous modules do.
|
# Suppressed warnings - 3009: Module 'blah' does not have a `timescale directive in effect, but previous modules do.
|
# Suppressed warnings - 8598: Non-positive replication multiplier inside concat. Replication will be ignored
|
# Suppressed warnings - 8598: Non-positive replication multiplier inside concat. Replication will be ignored
|
|
|
|
# - set GUI=1 if you want to invoke Modelsim GUI to debug
|
|
# - Propably you would like to switch off optimization
|
|
# also which will allow you to see all nets ...
|
|
#
|
|
ifeq ($(GUI), 1)
|
|
VSIM_ARGS+= -suppress 7 -suppress 3009 -suppress 8598 -novopt -do "set StdArithNoWarnings 1"
|
|
else
|
VSIM_ARGS+= -suppress 7 -suppress 3009 -suppress 8598 -c $(QUIET) -do "set StdArithNoWarnings 1; run -all; exit"
|
VSIM_ARGS+= -suppress 7 -suppress 3009 -suppress 8598 -c $(QUIET) -do "set StdArithNoWarnings 1; run -all; exit"
|
|
endif
|
|
|
# VPI debugging interface set up
|
# VPI debugging interface set up
|
VPI_SRC_C_DIR=$(COMMON_BENCH_VERILOG_DIR)/vpi/c
|
VPI_SRC_C_DIR=$(COMMON_BENCH_VERILOG_DIR)/vpi/c
|
VPI_SRCS=$(shell ls $(VPI_SRC_C_DIR)/*.[ch])
|
VPI_SRCS=$(shell ls $(VPI_SRC_C_DIR)/*.[ch])
|
|
|
| Line 59... |
Line 68... |
#
|
#
|
|
|
# Backend script generation - make these rules sensitive to source and includes
|
# Backend script generation - make these rules sensitive to source and includes
|
modelsim_backend.scr: $(BOARD_BACKEND_VERILOG_SRC)
|
modelsim_backend.scr: $(BOARD_BACKEND_VERILOG_SRC)
|
$(Q)echo "+incdir+"$(TECHNOLOGY_BACKEND_VERILOG_DIR) > $@;
|
$(Q)echo "+incdir+"$(TECHNOLOGY_BACKEND_VERILOG_DIR) > $@;
|
$(Q)echo "-y " $(BOARD_BACKEND_VERILOG_DIR) >> $@;
|
$(Q)echo "+incdir+"$(BOARD_BACKEND_VERILOG_SRC) >> $@;
|
|
$(Q)echo "+incdir+"$(BOARD_BENCH_VERILOG_DIR) > $@;
|
$(Q)for vsrc in $(BACKEND_TECHNOLOGY_VERILOG_SRC); do echo $$vsrc >> $@; done
|
$(Q)for vsrc in $(BACKEND_TECHNOLOGY_VERILOG_SRC); do echo $$vsrc >> $@; done
|
$(Q)echo "-y " $(TECHNOLOGY_LIBRARY_VERILOG_DIR) >> $@;
|
$(Q)echo "-y " $(TECHNOLOGY_LIBRARY_VERILOG_DIR) >> $@;
|
|
$(Q)for vsrc in $(BOARD_BACKEND_VERILOG_SRC); do echo $$vsrc >> $@; done
|
$(Q)echo "+libext+.v" >> $@;
|
$(Q)echo "+libext+.v" >> $@;
|
$(Q)echo >> $@;
|
$(Q)echo >> $@;
|
|
|
# DUT compile script
|
# DUT compile script
|
modelsim_dut.scr: $(RTL_VERILOG_SRC) $(RTL_VERILOG_INCLUDES) $(BOOTROM_VERILOG)
|
modelsim_dut.scr: $(RTL_VERILOG_SRC) $(RTL_VERILOG_INCLUDES) $(BOOTROM_VERILOG)
|
| Line 82... |
Line 93... |
fi
|
fi
|
ifeq ($(FPGA_VENDOR), xilinx)
|
ifeq ($(FPGA_VENDOR), xilinx)
|
$(Q)echo "-y "$(TECHNOLOGY_LIBRARY_VERILOG_DIR)"/src/unisims" >> $@;
|
$(Q)echo "-y "$(TECHNOLOGY_LIBRARY_VERILOG_DIR)"/src/unisims" >> $@;
|
$(Q)echo "-y "$(TECHNOLOGY_LIBRARY_VERILOG_DIR)"/src/XilinxCoreLib" >> $@;
|
$(Q)echo "-y "$(TECHNOLOGY_LIBRARY_VERILOG_DIR)"/src/XilinxCoreLib" >> $@;
|
endif
|
endif
|
$(Q)echo >> $@
|
ifeq ($(BOARD_NAME), ordb2a-ep4ce22)
|
|
$(Q)echo "../../rtl/verilog/versatile_library/versatile_library_ordbcycloneiv.v" >> $@;
|
|
endif
|
|
$(Q)echo >> $@;
|
|
|
modelsim_bench.scr: $(BOARD_BENCH_VERILOG_SRC) $(COMMON_BENCH_VERILOG_SRC)
|
modelsim_bench.scr: $(BOARD_BENCH_VERILOG_SRC) $(COMMON_BENCH_VERILOG_SRC)
|
$(Q)echo "+incdir+"$(BOARD_BENCH_VERILOG_INCLUDE_DIR) > $@;
|
$(Q)echo "+incdir+"$(BOARD_RTL_VERILOG_INCLUDE_DIR) > $@;
|
|
$(Q)echo "+incdir+"$(BOARD_BENCH_VERILOG_INCLUDE_DIR) >> $@;
|
$(Q)echo "+incdir+"$(COMMON_BENCH_VERILOG_INCLUDE_DIR) >> $@;
|
$(Q)echo "+incdir+"$(COMMON_BENCH_VERILOG_INCLUDE_DIR) >> $@;
|
$(Q)for path in $(BENCH_VERILOG_SUBDIRS); do echo "+incdir+"$$path >> $@; done
|
$(Q)for path in $(BENCH_VERILOG_SUBDIRS); do echo "+incdir+"$$path >> $@; done
|
$(Q)for path in $(BENCH_VERILOG_SUBDIRS); do echo "-y "$$path >> $@; done
|
$(Q)for path in $(BENCH_VERILOG_SUBDIRS); do echo "-y "$$path >> $@; done
|
$(Q)echo "+incdir+"$(BOARD_RTL_VERILOG_INCLUDE_DIR) >> $@;
|
$(Q)echo "+incdir+"$(BOARD_RTL_VERILOG_INCLUDE_DIR) >> $@;
|
$(Q)echo "+libext+.v" >> $@;
|
$(Q)echo "+libext+.v" >> $@;
|
| Line 150... |
Line 165... |
|
|
ifeq ($(FPGA_VENDOR), altera)
|
ifeq ($(FPGA_VENDOR), altera)
|
$(MODELSIM): modelsim_bench.scr $(TEST_DEFINES_VLG) $(BACKEND_LIB) $(VPI_LIBS) work
|
$(MODELSIM): modelsim_bench.scr $(TEST_DEFINES_VLG) $(BACKEND_LIB) $(VPI_LIBS) work
|
$(Q)echo; echo "\t### Compiling testbench ###"; echo
|
$(Q)echo; echo "\t### Compiling testbench ###"; echo
|
$(Q)vlog $(QUIET) -nologo -incr $(BENCH_TOP_FILE) -f $<
|
$(Q)vlog $(QUIET) -nologo -incr $(BENCH_TOP_FILE) -f $<
|
|
ifneq ($(MGC_NO_VOPT), 1)
|
|
$(Q)echo; echo "\t### Optimizing testbench ###"; echo
|
$(Q)$(MGC_VOPT_EXE) $(QUIET) $(RTL_TESTBENCH_TOP_NAME) $(VOPT_ARGS) -L $(BACKEND_LIB) -o tb
|
$(Q)$(MGC_VOPT_EXE) $(QUIET) $(RTL_TESTBENCH_TOP_NAME) $(VOPT_ARGS) -L $(BACKEND_LIB) -o tb
|
|
endif
|
$(Q)echo; echo "\t### Launching simulation ###"; echo
|
$(Q)echo; echo "\t### Launching simulation ###"; echo
|
$(Q)vsim $(VSIM_ARGS) $(MGC_VSIM_TGT)
|
$(Q)vsim $(QUIET) $(VSIM_ARGS) $(MGC_VSIM_TGT) -L $(BACKEND_LIB)
|
endif
|
endif
|
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|
No newline at end of file
|
