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# Modelsim script generation, compile and run rules for board simulations
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# Modelsim script generation, compile and run rules for board simulations
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#
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#
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# Modelsim-specific settings
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# Modelsim-specific settings
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#
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#
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VOPT_ARGS=$(QUIET) -suppress 2241
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VOPT_ARGS+=$(QUIET) -suppress 2241
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# If VCD dump is desired, tell Modelsim not to optimise
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# If VCD dump is desired, tell Modelsim not to optimise
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# away everything.
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# away everything.
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ifeq ($(VCD), 1)
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ifeq ($(VCD), 1)
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#VOPT_ARGS=-voptargs="+acc=rnp"
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#VOPT_ARGS=-voptargs="+acc=rnp"
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VOPT_ARGS=+acc=rnpqv
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VOPT_ARGS+=+acc=rnpqv
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endif
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endif
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# VSIM commands
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# VSIM commands
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# Suppressed warnings - 3009: Failed to open $readmemh() file
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# Suppressed warnings - 3009: Failed to open $readmemh() file
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# Suppressed warnings - 3009: Module 'blah' does not have a `timescale directive in effect, but previous modules do.
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# Suppressed warnings - 3009: Module 'blah' does not have a `timescale directive in effect, but previous modules do.
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# Suppressed warnings - 8598: Non-positive replication multiplier inside concat. Replication will be ignored
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# Suppressed warnings - 8598: Non-positive replication multiplier inside concat. Replication will be ignored
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VSIM_ARGS= -suppress 7 -suppress 3009 -suppress 8598 -c $(QUIET) -do "set StdArithNoWarnings 1; run -all; exit"
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VSIM_ARGS+= -suppress 7 -suppress 3009 -suppress 8598 -c $(QUIET) -do "set StdArithNoWarnings 1; run -all; exit"
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# VPI debugging interface set up
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# VPI debugging interface set up
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VPI_SRC_C_DIR=$(COMMON_BENCH_VERILOG_DIR)/vpi/c
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VPI_SRC_C_DIR=$(COMMON_BENCH_VERILOG_DIR)/vpi/c
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VPI_SRCS=$(shell ls $(VPI_SRC_C_DIR)/*.[ch])
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VPI_SRCS=$(shell ls $(VPI_SRC_C_DIR)/*.[ch])
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$(Q)if [ ! -z "$$GATELEVEL_MODULES" ]; \
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$(Q)if [ ! -z "$$GATELEVEL_MODULES" ]; \
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then echo "-y " $(BOARD_SYN_OUT_DIR) >> $@; \
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then echo "-y " $(BOARD_SYN_OUT_DIR) >> $@; \
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echo "+libext+.vm" >> $@; \
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echo "+libext+.vm" >> $@; \
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fi
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fi
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ifeq ($(FPGA_VENDOR), xilinx)
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ifeq ($(FPGA_VENDOR), xilinx)
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$(Q)echo "-y "$(XILINX_PATH)"/verilog/src/unisims" >> $@;
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$(Q)echo "-y "$(TECHNOLOGY_LIBRARY_VERILOG_DIR)"/src/unisims" >> $@;
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$(Q)echo "-y "$(XILINX_PATH)"/verilog/src/XilinxCoreLib" >> $@;
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$(Q)echo "-y "$(TECHNOLOGY_LIBRARY_VERILOG_DIR)"/src/XilinxCoreLib" >> $@;
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endif
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endif
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$(Q)echo >> $@
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$(Q)echo >> $@
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modelsim_bench.scr: $(BOARD_BENCH_VERILOG_SRC) $(COMMON_BENCH_VERILOG_SRC)
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modelsim_bench.scr: $(BOARD_BENCH_VERILOG_SRC) $(COMMON_BENCH_VERILOG_SRC)
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$(Q)echo "+incdir+"$(BOARD_BENCH_VERILOG_INCLUDE_DIR) > $@;
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$(Q)echo "+incdir+"$(BOARD_BENCH_VERILOG_INCLUDE_DIR) > $@;
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$(Q)echo "+incdir+"$(BOARD_RTL_VERILOG_INCLUDE_DIR) >> $@;
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$(Q)echo "+incdir+"$(BOARD_RTL_VERILOG_INCLUDE_DIR) >> $@;
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$(Q)echo "+libext+.v" >> $@;
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$(Q)echo "+libext+.v" >> $@;
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$(Q)for vsrc in $(BOARD_BENCH_VERILOG_SRC); do echo $$vsrc >> $@; done
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$(Q)for vsrc in $(BOARD_BENCH_VERILOG_SRC); do echo $$vsrc >> $@; done
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$(Q)for vsrc in $(COMMON_BENCH_VERILOG_SRC); do echo $$vsrc >> $@; done
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$(Q)for vsrc in $(COMMON_BENCH_VERILOG_SRC); do echo $$vsrc >> $@; done
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ifeq ($(FPGA_VENDOR), xilinx)
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ifeq ($(FPGA_VENDOR), xilinx)
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$(Q)echo "+incdir+"$(XILINX_PATH)"/verilog/src" >> $@;
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$(Q)echo "+incdir+"$(TECHNOLOGY_LIBRARY_VERILOG_DIR)"/src" >> $@;
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endif
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endif
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$(Q)echo >> $@
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$(Q)echo >> $@
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#
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#
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# Build rules
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# Build rules
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endif
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endif
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ifeq ($(FPGA_VENDOR), xilinx)
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ifeq ($(FPGA_VENDOR), xilinx)
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$(MODELSIM): modelsim_bench.scr $(TEST_DEFINES_VLG) $(VPI_LIBS) work
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$(MODELSIM): modelsim_bench.scr $(TEST_DEFINES_VLG) $(VPI_LIBS) work
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$(Q)echo; echo "\t### Compiling Xilinx support libs, user design & testbench ###"; echo
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$(Q)echo; echo "\t### Compiling Xilinx support libs, user design & testbench ###"; echo
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ifeq ($(DO_XILINX_COMPXLIB), 1)
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$(Q)$(TECHNOLOGY_BACKEND_BIN_DIR)/compxlib $(XLIB_ARGS)
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endif
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$(Q)vlog $(QUIET) -nologo -incr $(BENCH_TOP_FILE) -f $<
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$(Q)vlog $(QUIET) -nologo -incr $(BENCH_TOP_FILE) -f $<
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$(Q)vopt $(QUIET) glbl $(RTL_TESTBENCH_TOP_NAME) $(VOPT_ARGS) -o tb
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$(Q)vopt $(QUIET) glbl $(RTL_TESTBENCH_TOP_NAME) $(VOPT_ARGS) -o tb
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$(Q)echo; echo "\t### Launching simulation ###"; echo
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$(Q)echo; echo "\t### Launching simulation ###"; echo
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$(Q)vsim $(VSIM_ARGS) tb
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$(Q)vsim $(VSIM_ARGS) tb
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endif
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endif
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