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https://opencores.org/ocsvn/openrisc/openrisc/trunk
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Rev 563 |
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Line 5... |
#COMMON_RTL_VHDL_DIR = $(COMMON_RTL_DIR)/vhdl
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#COMMON_RTL_VHDL_DIR = $(COMMON_RTL_DIR)/vhdl
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BOARD_RTL_DIR=$(BOARD_ROOT)/rtl
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BOARD_RTL_DIR=$(BOARD_ROOT)/rtl
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BOARD_RTL_VERILOG_DIR=$(BOARD_RTL_DIR)/verilog
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BOARD_RTL_VERILOG_DIR=$(BOARD_RTL_DIR)/verilog
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#BOARD_RTL_VHDL_DIR = $(BOARD_RTL_DIR)/vhdl
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#BOARD_RTL_VHDL_DIR = $(BOARD_RTL_DIR)/vhdl
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BOARD_EXT_MODULES_DIR=$(BOARD_ROOT)/modules
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# Only 1 include path for board builds - their own!
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# Only 1 include path for board builds - their own!
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BOARD_RTL_VERILOG_INCLUDE_DIR=$(BOARD_RTL_VERILOG_DIR)/include
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BOARD_RTL_VERILOG_INCLUDE_DIR=$(BOARD_RTL_VERILOG_DIR)/include
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BOARD_BENCH_DIR=$(BOARD_ROOT)/bench
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BOARD_BENCH_DIR=$(BOARD_ROOT)/bench
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