URL
https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
Rev 542 |
Rev 563 |
Line 5... |
Line 5... |
#COMMON_RTL_VHDL_DIR = $(COMMON_RTL_DIR)/vhdl
|
#COMMON_RTL_VHDL_DIR = $(COMMON_RTL_DIR)/vhdl
|
|
|
BOARD_RTL_DIR=$(BOARD_ROOT)/rtl
|
BOARD_RTL_DIR=$(BOARD_ROOT)/rtl
|
BOARD_RTL_VERILOG_DIR=$(BOARD_RTL_DIR)/verilog
|
BOARD_RTL_VERILOG_DIR=$(BOARD_RTL_DIR)/verilog
|
#BOARD_RTL_VHDL_DIR = $(BOARD_RTL_DIR)/vhdl
|
#BOARD_RTL_VHDL_DIR = $(BOARD_RTL_DIR)/vhdl
|
|
BOARD_EXT_MODULES_DIR=$(BOARD_ROOT)/modules
|
|
|
# Only 1 include path for board builds - their own!
|
# Only 1 include path for board builds - their own!
|
BOARD_RTL_VERILOG_INCLUDE_DIR=$(BOARD_RTL_VERILOG_DIR)/include
|
BOARD_RTL_VERILOG_INCLUDE_DIR=$(BOARD_RTL_VERILOG_DIR)/include
|
|
|
BOARD_BENCH_DIR=$(BOARD_ROOT)/bench
|
BOARD_BENCH_DIR=$(BOARD_ROOT)/bench
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.