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Line 8... |
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# Paths under board/***/rtl/verilog we wish to exclude when getting modules
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# Paths under board/***/rtl/verilog we wish to exclude when getting modules
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BOARD_VERILOG_MODULES_EXCLUDE += include
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BOARD_VERILOG_MODULES_EXCLUDE += include
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BOARD_VERILOG_MODULES_EXCLUDE += $(GATELEVEL_MODULES)
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BOARD_VERILOG_MODULES_EXCLUDE += $(GATELEVEL_MODULES)
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BOARD_VERILOG_MODULES_DIR_LIST=$(shell ls $(BOARD_RTL_VERILOG_DIR))
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BOARD_VERILOG_MODULES_DIR_LIST=$(shell ls $(BOARD_RTL_VERILOG_DIR))
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BOARD_EXT_MODULES_DIR_LIST=$(shell ls $(BOARD_EXT_MODULES_DIR))
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# Apply exclude to list of modules
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# Apply exclude to list of modules
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BOARD_RTL_VERILOG_MODULES=$(filter-out $(BOARD_VERILOG_MODULES_EXCLUDE),$(BOARD_VERILOG_MODULES_DIR_LIST))
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BOARD_RTL_VERILOG_MODULES=$(filter-out $(BOARD_VERILOG_MODULES_EXCLUDE),$(BOARD_VERILOG_MODULES_DIR_LIST))
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BOARD_EXT_MODULES=$(filter-out $(BOARD_VERILOG_MODULES_EXCLUDE),$(BOARD_EXT_MODULES_DIR_LIST))
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# Now get list of modules that we don't have a version of in the board path
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# Now get list of modules that we don't have a version of in the board path
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COMMON_VERILOG_MODULES_EXCLUDE += include
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COMMON_VERILOG_MODULES_EXCLUDE += include
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COMMON_VERILOG_MODULES_EXCLUDE += $(BOARD_RTL_VERILOG_MODULES)
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COMMON_VERILOG_MODULES_EXCLUDE += $(BOARD_RTL_VERILOG_MODULES)
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COMMON_VERILOG_MODULES_EXCLUDE += $(BOARD_EXT_MODULES)
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COMMON_VERILOG_MODULES_EXCLUDE += $(GATELEVEL_MODULES)
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COMMON_VERILOG_MODULES_EXCLUDE += $(GATELEVEL_MODULES)
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COMMON_RTL_VERILOG_MODULES_DIR_LIST=$(shell ls $(COMMON_RTL_VERILOG_DIR))
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COMMON_RTL_VERILOG_MODULES_DIR_LIST=$(shell ls $(COMMON_RTL_VERILOG_DIR))
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COMMON_RTL_VERILOG_MODULES=$(filter-out $(COMMON_VERILOG_MODULES_EXCLUDE), $(COMMON_RTL_VERILOG_MODULES_DIR_LIST))
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COMMON_RTL_VERILOG_MODULES=$(filter-out $(COMMON_VERILOG_MODULES_EXCLUDE), $(COMMON_RTL_VERILOG_MODULES_DIR_LIST))
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# List of verilog source files (only .v files!)
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# List of verilog source files (only .v files!)
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# Board RTL modules first
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# Board RTL modules first
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RTL_VERILOG_SRC=$(shell for module in $(BOARD_RTL_VERILOG_MODULES); do if [ -d $(BOARD_RTL_VERILOG_DIR)/$$module ]; then ls $(BOARD_RTL_VERILOG_DIR)/$$module/*.v; fi; done)
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RTL_VERILOG_SRC=$(shell for module in $(BOARD_RTL_VERILOG_MODULES); do if [ -d $(BOARD_RTL_VERILOG_DIR)/$$module ]; then ls $(BOARD_RTL_VERILOG_DIR)/$$module/*.v; fi; done)
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# External modules
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RTL_VERILOG_SRC +=$(shell for module in $(BOARD_EXT_MODULES); do if [ -d $(BOARD_EXT_MODULES_DIR)/$$module/rtl/verilog ]; then ls $(BOARD_EXT_MODULES_DIR)/$$module/rtl/verilog/*.v; fi; done)
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# Common RTL module source
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# Common RTL module source
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RTL_VERILOG_SRC +=$(shell for module in $(COMMON_RTL_VERILOG_MODULES); do if [ -d $(COMMON_RTL_VERILOG_DIR)/$$module ]; then ls $(COMMON_RTL_VERILOG_DIR)/$$module/*.v; fi; done)
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RTL_VERILOG_SRC +=$(shell for module in $(COMMON_RTL_VERILOG_MODULES); do if [ -d $(COMMON_RTL_VERILOG_DIR)/$$module ]; then ls $(COMMON_RTL_VERILOG_DIR)/$$module/*.v; fi; done)
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# List of verilog includes from board RTL path - only for rule sensitivity
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# List of verilog includes from board RTL path - only for rule sensitivity
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RTL_VERILOG_INCLUDES=$(shell ls $(BOARD_RTL_VERILOG_INCLUDE_DIR)/*.*)
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RTL_VERILOG_INCLUDES=$(shell ls $(BOARD_RTL_VERILOG_INCLUDE_DIR)/*.*)
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# Debugging rules
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# Debugging rules
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print-board-modules:
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print-board-modules:
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@echo echo; echo "\t### Board verilog modules ###"; echo
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@echo echo; echo "\t### Board verilog modules ###"; echo
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@echo $(BOARD_RTL_VERILOG_MODULES)
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@echo $(BOARD_RTL_VERILOG_MODULES)
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@echo echo "\t### External verilog modules ###"; echo
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@echo $(BOARD_EXT_MODULES)
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print-common-modules-exclude:
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print-common-modules-exclude:
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@echo echo; echo "\t### Common verilog modules being excluded due to board versions ###"; echo
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@echo echo; echo "\t### Common verilog modules being excluded due to board versions ###"; echo
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@echo "$(COMMON_VERILOG_MODULES_EXCLUDE)"
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@echo "$(COMMON_VERILOG_MODULES_EXCLUDE)"
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