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Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [scripts/] [make/] [Makefile-board-rtlmodules.inc] - Diff between revs 542 and 558

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Rev 542 Rev 558
Line 45... Line 45...
        @echo $(COMMON_RTL_VERILOG_MODULES)
        @echo $(COMMON_RTL_VERILOG_MODULES)
 
 
print-verilog-src:
print-verilog-src:
        @echo echo; echo "\t### Verilog source ###"; echo
        @echo echo; echo "\t### Verilog source ###"; echo
        @echo $(RTL_VERILOG_SRC)
        @echo $(RTL_VERILOG_SRC)
 
 
 
 
 
ifeq ($(HAVE_VHDL), 1)
 
# We have some VHDL we should include.
 
 
 
# Currently only supported for board builds - no common VHDL included at present
 
BOARD_RTL_VHDL_DIR=$(BOARD_RTL_DIR)/vhdl
 
BOARD_RTL_VHDL_MODULES=$(shell ls $(BOARD_RTL_VHDL_DIR))
 
 
 
#
 
# VHDL DUT source variables
 
#
 
VHDL_FILE_EXT=vhd
 
 
 
RTL_VHDL_SRC=$(shell for module in $(BOARD_RTL_VHDL_MODULES); do if [ -d $(BOARD_RTL_VHDL_DIR)/$$module ]; then ls $(BOARD_RTL_VHDL_DIR)/$$module/*.$(VHDL_FILE_EXT); fi; done)
 
 
 
 
 
# Rule for debugging this script
 
print-vhdl-modules:
 
        @echo echo; echo "\t### Board VHDL modules ###"; echo
 
        @echo $(BOARD_RTL_VHDL_MODULES)
 
 
 
print-vhdl-src:
 
        @echo echo; echo "\t### VHDL modules and source ###"; echo
 
        @echo "modules: "; echo $(BOARD_RTL_VHDL_MODULES); echo
 
        @echo "file extension: "$(VHDL_FILE_EXT)
 
        @echo "source: "$(RTL_VHDL_SRC)
 
 
 
 
 
endif
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