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# Variables holding the names and paths to top-level files
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# Variables holding the names and paths to top-level files
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# Name of testbench top
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# Name of testbench top
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RTL_TESTBENCH_TOP=$(DESIGN_NAME)_testbench
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RTL_TESTBENCH_TOP_NAME=$(DESIGN_NAME)_testbench
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# Paths to top-level files
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# Paths to top-level files
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DUT_TOP=$(BOARD_RTL_VERILOG_DIR)/$(DESIGN_NAME)_top/$(DESIGN_NAME)_top.v
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DUT_TOP_FILE=$(BOARD_RTL_VERILOG_DIR)/$(DESIGN_NAME)_top/$(DESIGN_NAME)_top.v
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BENCH_TOP=$(BOARD_BENCH_VERILOG_DIR)/$(DESIGN_NAME)_testbench.v
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BENCH_TOP_FILE=$(BOARD_BENCH_VERILOG_DIR)/$(DESIGN_NAME)_testbench.v
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BENCH_TOP_FILE=$(BOARD_BENCH_VERILOG_DIR)/$(DESIGN_NAME)_testbench.v
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BENCH_TOP_FILE=$(BOARD_BENCH_VERILOG_DIR)/$(DESIGN_NAME)_testbench.v
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