| Line 433... |
Line 433... |
$(MAKE) -C $(BOOTROM_SW_DIR) clean
|
$(MAKE) -C $(BOOTROM_SW_DIR) clean
|
|
|
clean-out:
|
clean-out:
|
$(Q)rm -rf $(RTL_SIM_RESULTS_DIR)/*.*
|
$(Q)rm -rf $(RTL_SIM_RESULTS_DIR)/*.*
|
|
|
|
# Clean away verilator build path and objects in SystemC path
|
clean-vlt:
|
clean-vlt:
|
$(Q)rm -rf $(SIM_VLT_DIR)
|
$(Q)rm -rf $(SIM_VLT_DIR)
|
|
$(Q)$(MAKE) -C $(BENCH_SYSC_SRC_DIR) -f $(BENCH_SYSC_SRC_DIR)/Modules.make clean
|
|
|
clean-test-defines:
|
clean-test-defines:
|
$(Q)rm -f $(TEST_DEFINES_VLG)
|
$(Q)rm -f $(TEST_DEFINES_VLG)
|
|
|
clean-sim-test-sw:
|
clean-sim-test-sw:
|
$(Q)if [ -e $(SIM_SW_IMAGE) ]; then unlink $(SIM_SW_IMAGE); fi
|
$(Q)if [ -e $(SIM_SW_IMAGE) ]; then unlink $(SIM_SW_IMAGE); fi
|
|
|
clean-sw:
|
clean-sw:
|
$(Q) echo; echo "\t### Cleaning simulation sw directories ###"; echo;
|
$(Q) echo; echo "\t### Cleaning simulation sw directories ###"; echo;
|
$(Q) $(MAKE) -C $(SW_DIR)/support distclean
|
$(Q) $(MAKE) -C $(SW_DIR)/or1200 clean-all
|
|
|
clean-rtl:
|
clean-rtl:
|
$(Q) echo; echo "\t### Cleaning generated verilog RTL ###"; echo;
|
$(Q) echo; echo "\t### Cleaning generated verilog RTL ###"; echo;
|
for module in $(RTL_TO_CHECK); do \
|
for module in $(RTL_TO_CHECK); do \
|
$(MAKE) -C $(RTL_VERILOG_DIR)/$$module clean; \
|
$(MAKE) -C $(RTL_VERILOG_DIR)/$$module clean; \
|
| Line 486... |
Line 488... |
|
|
# List of System C models - use this list to link the sources into the Verilator
|
# List of System C models - use this list to link the sources into the Verilator
|
# build directory
|
# build directory
|
SYSC_MODELS=OrpsocAccess MemoryLoad
|
SYSC_MODELS=OrpsocAccess MemoryLoad
|
|
|
|
ifdef VLT_LINT
|
|
VLT_FLAGS +=--lint-only
|
|
endif
|
|
|
ifdef VLT_DEBUG
|
ifdef VLT_DEBUG
|
VLT_DEBUG_COMPILE_FLAGS = -g
|
VLT_DEBUG_COMPILE_FLAGS = -g
|
# Enabling the following generates a TON of debugging
|
# Enabling the following generates a TON of debugging
|
# when running verilator. Not so helpful.
|
# when running verilator. Not so helpful.
|
#VLT_DEBUG_OPTIONS = --debug --dump-tree
|
#VLT_FLAGS = --debug --dump-tree
|
VLT_SYSC_DEBUG_DEFINE = VLT_DEBUG=1
|
VLT_SYSC_DEBUG_DEFINE = VLT_DEBUG=1
|
endif
|
endif
|
|
|
# If set on the command line we build the cycle accurate model which will generate verilator-specific profiling information. This is useful for checking the efficiency of the model - not really useful for checking code or the function of the model.
|
# This will build a verilator model that will generate profiling information
|
ifdef VLT_ORPSOC_PROFILING
|
# suitable for gprof
|
VLT_CPPFLAGS +=-pg
|
# Run it through gprof after exection with: gprof Vorpsoc_top > gprof.out
|
VLT_DEBUG_OPTIONS +=-profile-cfuncs
|
# then run this through the Verilator tool with:
|
|
# verilator_profcfunc gprof.out > vprof.out
|
|
ifdef VLT_EXECUTION_PROFILE_BUILD
|
|
VLT_CPPFLAGS +=-g -pg
|
|
# Maybe add these to VLT_CPPFLAGS: -ftest-coverage -fprofile-arcs
|
|
VLT_FLAGS +=-profile-cfuncs
|
|
endif
|
|
|
|
# If set on the command line we build the cycle accurate model which will
|
|
# generate verilator-specific profiling information. This is useful for
|
|
# checking the efficiency of the model - not really useful for checking code
|
|
# or the function of the model.
|
|
ifdef VLT_DO_PERFORMANCE_PROFILE_BUILD
|
|
VLT_CPPFLAGS += -fprofile-generate -fbranch-probabilities -fvpt -funroll-loops -fpeel-loops -ftracer
|
else
|
else
|
VLT_CPPFLAGS +=-fprofile-use -Wcoverage-mismatch
|
VLT_CPPFLAGS +=-fprofile-use -Wcoverage-mismatch
|
#VLT_CPPFLAGS=-Wall
|
|
endif
|
endif
|
|
|
# Set VLT_IN_GDB=1 when making if going to run the cycle accurate model executable in GDB to check suspect behavior. This also removes optimisation.
|
# Set VLT_IN_GDB=1 when making if going to run the cycle accurate model
|
|
# executable in GDB.
|
ifdef VLT_IN_GDB
|
ifdef VLT_IN_GDB
|
VLT_CPPFLAGS +=-g -O0
|
VLT_CPPFLAGS +=-g -O0
|
else
|
else
|
# The default optimisation flag applied to all of the cycle accurate model files
|
# The default optimisation flag applied to all of the cycle accurate model files
|
VLT_CPPFLAGS +=-O3
|
VLT_CPPFLAGS +=-O3
|
endif
|
endif
|
|
|
ifdef VLT_DO_PROFILING
|
|
VLT_CPPFLAGS +=-ftest-coverage -fprofile-arcs -fprofile-generate
|
|
endif
|
|
|
|
# VCD Enabled by default when building, enable it at runtime
|
# VCD Enabled by default when building, enable it at runtime
|
#ifdef VCD
|
|
VLT_FLAGS +=-trace
|
VLT_FLAGS +=-trace
|
TRACE_FLAGS=-DVM_TRACE=1 -I${SYSTEMPERL}/src
|
TRACE_FLAGS=-DVM_TRACE=1 -I${SYSTEMPERL}/src
|
#endif
|
|
|
|
# Only need the trace target if we are tracing
|
# Verilator tuning
|
#ifneq (,$(findstring -trace, $(VLT_FLAGS)))
|
# Inlining:
|
|
VLT_FLAGS +=--inline-mult 1
|
|
# Optimisation option for Verilator scripts
|
|
VLT_FLAGS +=-O3
|
|
# X-assign - at reset, all signals are set to random values, helps find rst bugs
|
|
VLT_FLAGS +=-x-assign unique
|
|
|
VLT_TRACEOBJ = verilated_vcd_c
|
VLT_TRACEOBJ = verilated_vcd_c
|
#endif
|
|
|
|
# This is the list of extra models we'll issue make commands for
|
# This is the list of extra models we'll issue make commands for
|
# Included is the SystemPerl trace model
|
# Included is the SystemPerl trace model
|
SYSC_MODELS_BUILD=$(SYSC_MODELS) $(VLT_TRACEOBJ)
|
SYSC_MODELS_BUILD=$(SYSC_MODELS) $(VLT_TRACEOBJ)
|
|
|
| Line 610... |
Line 629... |
|
|
$(SIM_VLT_DIR)/$(VLT_EXE).mk: $(SIM_VLT_DIR)/$(VLT_SCRIPT) $(BENCH_SYSC_SRC_DIR)/libmodules.a
|
$(SIM_VLT_DIR)/$(VLT_EXE).mk: $(SIM_VLT_DIR)/$(VLT_SCRIPT) $(BENCH_SYSC_SRC_DIR)/libmodules.a
|
# Now call verilator to generate the .mk files
|
# Now call verilator to generate the .mk files
|
$(Q)echo; echo "\tGenerating makefiles with Verilator"; echo
|
$(Q)echo; echo "\tGenerating makefiles with Verilator"; echo
|
$(Q)cd $(SIM_VLT_DIR) && \
|
$(Q)cd $(SIM_VLT_DIR) && \
|
verilator -language 1364-2001 -Wno-lint --top-module orpsoc_top $(VLT_DEBUG_OPTIONS) -Mdir . -sc $(VLT_FLAGS) -I$(BENCH_SYSC_INCLUDE_DIR) -I$(BENCH_SYSC_SRC_DIR) -f $(SIM_VLT_DIR)/$(VLT_SCRIPT)
|
verilator -language 1364-2001 --top-module orpsoc_top -Mdir . -sc $(VLT_FLAGS) -I$(BENCH_SYSC_INCLUDE_DIR) -I$(BENCH_SYSC_SRC_DIR) -f $(SIM_VLT_DIR)/$(VLT_SCRIPT)
|
|
|
# SystemC modules library
|
# SystemC modules library
|
$(BENCH_SYSC_SRC_DIR)/libmodules.a:
|
$(BENCH_SYSC_SRC_DIR)/libmodules.a:
|
@echo; echo "\tCompiling SystemC modules"; echo
|
@echo; echo "\tCompiling SystemC modules"; echo
|
$(Q)export VLT_CPPFLAGS="$(VLT_CPPFLAGS)"; \
|
$(Q)export VLT_CPPFLAGS="$(VLT_CPPFLAGS)"; \
|
| Line 658... |
Line 677... |
# "make clean" and then a "make prepare-vlt_profiled"
|
# "make clean" and then a "make prepare-vlt_profiled"
|
# This new make target copies athe results of the profiling back to the right
|
# This new make target copies athe results of the profiling back to the right
|
# paths before we create everything again
|
# paths before we create everything again
|
###############################################################################
|
###############################################################################
|
.PHONY: prepare-vlt-profiled
|
.PHONY: prepare-vlt-profiled
|
prepare-vlt-profiled: $(SIM_VLT_DIR)/OrpsocMain.gcda clean vlt-restore-profileoutput rtl $(SIM_VLT_DIR) $(DUMMY_FILES_FOR_VLT) $(VLT_MODEL_LINKS) $(SIM_VLT_DIR)/$(VLT_EXE)
|
prepare-vlt-profiled: $(SIM_VLT_DIR)/OrpsocMain.gcda \
|
|
clean-vlt-after-profile-run \
|
|
rtl $(SIM_VLT_DIR) $(DUMMY_FILES_FOR_VLT) $(VLT_MODEL_LINKS) \
|
|
$(SIM_VLT_DIR)/$(VLT_EXE)
|
|
|
$(SIM_VLT_DIR)/OrpsocMain.gcda: $(SIM_VLT_DIR)/$(VLT_EXE)-for-profiling
|
$(SIM_VLT_DIR)/OrpsocMain.gcda: $(SIM_VLT_DIR)/$(VLT_EXE)-for-profiling
|
$(MAKE) -C $(SW_DIR)/dhry dhry.elf NUM_RUNS=200
|
$(MAKE) -C $(SW_DIR)/dhry dhry.elf NUM_RUNS=5000
|
$(SIM_VLT_DIR)/$(VLT_EXE) -f $(SW_DIR)/dhry/dhry.elf -v -l sim.log --crash-monitor
|
# $(SIM_VLT_DIR)/$(VLT_EXE) -f $(SW_DIR)/dhry/dhry.elf -v -l sim.log --crash-monitor
|
|
$(SIM_VLT_DIR)/$(VLT_EXE) -f $(SW_DIR)/dhry/dhry.elf
|
|
|
|
# Clean all compiled things
|
|
clean-vlt-after-profile-run:
|
|
$(Q)echo "\tCleaning away compiled cycle-accurate files"
|
|
$(Q)rm -f $(SIM_VLT_DIR)/*.[oa] $(SIM_VLT_DIR)/$(VLT_EXE)
|
|
$(Q)rm -f $(BENCH_SYSC_SRC_DIR)/*.[oa]
|
|
|
.PHONY: $(SIM_VLT_DIR)/$(VLT_EXE)-for-profiling
|
#.PHONY: $(SIM_VLT_DIR)/$(VLT_EXE)-for-profiling
|
$(SIM_VLT_DIR)/$(VLT_EXE)-for-profiling:
|
$(SIM_VLT_DIR)/$(VLT_EXE)-for-profiling:
|
$(MAKE) prepare-vlt VLT_DO_PROFILING=1
|
$(MAKE) build-vlt VLT_DO_PERFORMANCE_PROFILE_BUILD=1
|
|
|
.PHONY: vlt-restore-profileoutput
|
.PHONY: vlt-restore-profileoutput
|
vlt-restore-profileoutput:
|
vlt-restore-profileoutput:
|
@echo;echo "\tRestoring profiling outputs"; echo
|
@echo;echo "\tRestoring profiling outputs"; echo
|
$(Q)mkdir -p ../vlt
|
$(Q)mkdir -p ../vlt
|
$(Q)cp /tmp/*.gc* $(SIM_VLT_DIR)
|
$(Q)cp /tmp/*.gc* $(SIM_VLT_DIR)
|
$(Q)cp /tmp/*.gc* $(BENCH_SYSC_SRC_DIR)
|
$(Q)cp /tmp/*.gc* $(BENCH_SYSC_SRC_DIR)
|
|
|
|
|
|
lint-vlt: $(SIM_VLT_DIR) rtl $(DUMMY_FILES_FOR_VLT) $(SIM_VLT_DIR)/$(VLT_SCRIPT)
|
|
$(Q)echo; echo "\tLinting design with Verilator"; echo
|
|
$(Q)cd $(SIM_VLT_DIR) && \
|
|
verilator -language 1364-2001 --top-module orpsoc_top --lint-only -Mdir . -sc $(VLT_FLAGS) -I$(BENCH_SYSC_INCLUDE_DIR) -I$(BENCH_SYSC_SRC_DIR) -f $(SIM_VLT_DIR)/$(VLT_SCRIPT)
|
No newline at end of file
|
No newline at end of file
|
