| Line 53... |
Line 53... |
BENCH_TOP=$(BENCH_VERILOG_DIR)/$(DESIGN_NAME)_testbench.v
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BENCH_TOP=$(BENCH_VERILOG_DIR)/$(DESIGN_NAME)_testbench.v
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# Need this for individual test variables to not break
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# Need this for individual test variables to not break
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TEST ?= or1200-simple
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TEST ?= or1200-simple
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TESTS ?= or1200-simple or1200-cbasic or1200-dctest or1200-float or1200-mmu or1200asm-basic or1200asm-except or1200asm-mac or1200asm-linkregtest or1200asm-tick or1200asm-ticksyscall uart-simple
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TESTS ?= or1200-simple or1200-basic or1200-cbasic or1200-dctest or1200-float or1200-mmu or1200-except or1200-mac or1200-linkregtest or1200-tick or1200-ticksyscall uart-simple
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# Gets turned into verilog `define
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# Gets turned into verilog `define
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SIM_TYPE=RTL
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SIM_TYPE=RTL
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# Paths to other important parts of this test suite
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# Paths to other important parts of this test suite
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| Line 386... |
Line 386... |
# $(Q)for module in $(GATELEVEL_MODULES); do echo "\`define "$$module"_IS_GATELEVEL " >> $@; done
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# $(Q)for module in $(GATELEVEL_MODULES); do echo "\`define "$$module"_IS_GATELEVEL " >> $@; done
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# More possible test defines go here
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# More possible test defines go here
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# Software make rules (called recursively)
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# Software make rules (called recursively)
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TEST_SW_DIR=$(SW_DIR)/$(shell echo $(TEST) | cut -d "-" -f 1)
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TEST_SW_DIR=$(SW_DIR)/tests/$(shell echo $(TEST) | cut -d "-" -f 1)/sim
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# Set PRELOAD_RAM=1 to preload the system memory, avoiding lengthy SPI FLASH
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# Set PRELOAD_RAM=1 to preload the system memory, avoiding lengthy SPI FLASH
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# bootloader process.
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# bootloader process.
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#ifeq ($(PRELOAD_RAM), 1)
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#ifeq ($(PRELOAD_RAM), 1)
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SIM_SW_IMAGE ?=sram.vmem
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SIM_SW_IMAGE ?=sram.vmem
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| Line 446... |
Line 446... |
clean-sim-test-sw:
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clean-sim-test-sw:
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$(Q)if [ -e $(SIM_SW_IMAGE) ]; then unlink $(SIM_SW_IMAGE); fi
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$(Q)if [ -e $(SIM_SW_IMAGE) ]; then unlink $(SIM_SW_IMAGE); fi
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clean-sw:
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clean-sw:
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$(Q) echo; echo "\t### Cleaning simulation sw directories ###"; echo;
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$(Q) echo; echo "\t### Cleaning simulation sw directories ###"; echo;
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$(Q) $(MAKE) -C $(SW_DIR)/or1200 clean-all
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$(Q) $(MAKE) -C $(SW_DIR)/lib clean-all
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clean-rtl:
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clean-rtl:
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$(Q) echo; echo "\t### Cleaning generated verilog RTL ###"; echo;
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$(Q) echo; echo "\t### Cleaning generated verilog RTL ###"; echo;
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for module in $(RTL_TO_CHECK); do \
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for module in $(RTL_TO_CHECK); do \
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$(MAKE) -C $(RTL_VERILOG_DIR)/$$module clean; \
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$(MAKE) -C $(RTL_VERILOG_DIR)/$$module clean; \
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