OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sim/] [bin/] [Makefile] - Diff between revs 393 and 397

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 393 Rev 397
Line 141... Line 141... 
 
 
 
 
SIMULATOR ?= $(ICARUS)
 
SIMULATOR ?= $(ICARUS)
 
 
 
 
 
# VPI debugging interface variables
 
# VPI debugging interface variables
 
VPI_SRC_C_DIR=$(BENCH_VERILOG_DIR)/vpi/c
 
VPI_SRC_C_DIR=$(BENCH_VERILOG_DIR)/vpi/c
 
 
 
VPI_SRC_VERILOG_DIR=$(BENCH_VERILOG_DIR)/vpi/verilog
 
VPI_SRCS=$(shell ls $(VPI_SRC_C_DIR)/*.[ch])
 
VPI_SRCS=$(shell ls $(VPI_SRC_C_DIR)/*.[ch])
 
 
 
 
 
# Modelsim VPI compile variables
 
# Modelsim VPI compile variables
 
MODELTECH_VPILIB=msim_jp_vpi.sl
 
MODELTECH_VPILIB=msim_jp_vpi.sl
 
# Icarus VPI compile target
 
# Icarus VPI compile target
Line 162... Line 163... 
endif
 
endif
 
# VSIM commands
 
# VSIM commands
 
# Suppressed warnings - 3009: Failed to open $readmemh() file
 
# Suppressed warnings - 3009: Failed to open $readmemh() file
 
# Suppressed warnings - 3009: Module 'blah' does not have a `timescale directive in effect, but previous modules do.
 
# Suppressed warnings - 3009: Module 'blah' does not have a `timescale directive in effect, but previous modules do.
 
# Suppressed warnings - 8598: Non-positive replication multiplier inside concat. Replication will be ignored
 
# Suppressed warnings - 8598: Non-positive replication multiplier inside concat. Replication will be ignored
 
VSIM_ARGS=  -suppress 7 -suppress 3009 -suppress 8598 -c $(QUIET) -do "set StdArithNoWarnings 1; run -all; exit"
 
MGC_VSIM_ARGS=  -suppress 7 -suppress 3009 -suppress 8598 -c $(QUIET) -do "set StdArithNoWarnings 1; run -all; exit"
 
# Modelsim VPI settings
 
# Options required when VPI option used
 
ifeq ($(VPI), 1)
 
ifeq ($(VPI), 1)
 
VPI_LIBS=$(VPI_SRC_C_DIR)/$(MODELTECH_VPILIB)
 
MGC_VPI_LIB=$(VPI_SRC_C_DIR)/$(MODELTECH_VPILIB)
 
VSIM_ARGS += -pli $(VPI_SRC_C_DIR)/$(MODELTECH_VPILIB)
 
MGC_VSIM_ARGS += -pli $(VPI_SRC_C_DIR)/$(MODELTECH_VPILIB)
 
 
 
 
 
 
 
ICARUS_VPI_LIB=$(VPI_SRC_C_DIR)/$(ICARUS_VPILIB)
 
 
 
ICARUS_VPI_ARGS=-M$(VPI_SRC_C_DIR) -m$(ICARUS_VPILIB)
 
endif
 
endif
 
# Rule to make the VPI library for modelsim
 
# Rule to make the VPI library for Modelsim
 
$(VPI_SRC_C_DIR)/$(MODELTECH_VPILIB): $(VPI_SRCS)
 
$(MGC_VPI_LIB): $(VPI_SRCS)
 
        $(MAKE) -C $(VPI_SRC_C_DIR) $(MODELTECH_VPILIB)
 
        $(MAKE) -C $(VPI_SRC_C_DIR) $(MODELTECH_VPILIB)
 
 
 
 
 
#
 
# Rule to make VPI library for Icarus Verilog
 
# Icarus Verilog-specific settings
 
$(ICARUS_VPI_LIB): $(VPI_SRCS)
 
#
 
 
 
 
 
 
 
# Rule to make the VPI library for Icarus
 
 
 
$(VPI_SRC_C_DIR)/$(ICARUS_VPILIB): $(VPI_SRCS)
 
 
 
        $(MAKE) -C $(VPI_SRC_C_DIR) $(ICARUS_VPILIB)
 
        $(MAKE) -C $(VPI_SRC_C_DIR) $(ICARUS_VPILIB)
 
 
 
 
 
 
 
# Manually add the VPI bench verilog path
 
 
 
BENCH_VERILOG_SRC_SUBDIRS += $(VPI_SRC_VERILOG_DIR)
 
 
 
 
 
#
 
#
 
# Verilog DUT source variables
 
# Verilog DUT source variables
 
#
 
#
 
# A list of paths under rtl/verilog we wish to exclude for module searching
 
# A list of paths under rtl/verilog we wish to exclude for module searching
 
VERILOG_MODULES_EXCLUDE=  include components
 
VERILOG_MODULES_EXCLUDE=  include components
Line 235... Line 238... 
print-bench-src:
 
print-bench-src:
 
        $(Q)echo "\tBench verilog source"; \
 
        $(Q)echo "\tBench verilog source"; \
 
        echo $(BENCH_VERILOG_SRC)
 
        echo $(BENCH_VERILOG_SRC)
 
 
 
 
 
# Testbench source subdirectory detection
 
# Testbench source subdirectory detection
 
BENCH_VERILOG_SRC_SUBDIRS=$(shell for file in `ls $(BENCH_VERILOG_DIR)`; do if [ -d $(BENCH_VERILOG_DIR)/$$file ]; then echo $(BENCH_VERILOG_DIR)/$$file; fi; done)
 
BENCH_VERILOG_SRC_SUBDIRS +=$(shell for file in `ls $(BENCH_VERILOG_DIR)`; do if [ -d $(BENCH_VERILOG_DIR)/$$file ]; then echo $(BENCH_VERILOG_DIR)/$$file; fi; done)
 
 
 
 
 
# Compile script generation rules:
 
# Compile script generation rules:
 
 
 
 
 
modelsim_dut.scr: rtl $(RTL_VERILOG_SRC) $(RTL_VERILOG_INCLUDES) $(BOOTROM_VERILOG)
 
modelsim_dut.scr: rtl $(RTL_VERILOG_SRC) $(RTL_VERILOG_INCLUDES) $(BOOTROM_VERILOG)
 
        $(Q)echo "+incdir+"$(RTL_VERILOG_INCLUDE_DIR) > $@;
 
        $(Q)echo "+incdir+"$(RTL_VERILOG_INCLUDE_DIR) > $@;
Line 269... Line 272... 
        $(Q)echo; echo "\t### Compiling Verilog design library ###"; echo
 
        $(Q)echo; echo "\t### Compiling Verilog design library ###"; echo
 
        $(Q)vlog $(QUIET) -f $< $(DUT_TOP)
 
        $(Q)vlog $(QUIET) -f $< $(DUT_TOP)
 
 
 
 
 
# Single compile rule
 
# Single compile rule
 
.PHONY : $(MODELSIM)
 
.PHONY : $(MODELSIM)
 
$(MODELSIM): modelsim_bench.scr $(TEST_DEFINES_VLG) $(VPI_LIBS) work
 
$(MODELSIM): modelsim_bench.scr $(TEST_DEFINES_VLG) $(MGC_VPI_LIB) work
 
        $(Q)echo; echo "\t### Compiling testbench ###"; echo
 
        $(Q)echo; echo "\t### Compiling testbench ###"; echo
 
        $(Q)vlog $(QUIET) -nologo -incr $(BENCH_TOP) -f $<
 
        $(Q)vlog $(QUIET) -nologo -incr $(BENCH_TOP) -f $<
 
        $(Q)vopt $(QUIET) $(RTL_TESTBENCH_TOP) $(VOPT_ARGS) -o tb
 
        $(Q)vopt $(QUIET) $(RTL_TESTBENCH_TOP) $(VOPT_ARGS) -o tb
 
        $(Q)echo; echo "\t### Launching simulation ###"; echo
 
        $(Q)echo; echo "\t### Launching simulation ###"; echo
 
        $(Q)vsim $(VSIM_ARGS) tb
 
        $(Q)vsim $(MGC_VSIM_ARGS) tb
 
 
 
 
 
#
 
#
 
# Icarus Verilog simulator build and run rules
 
# Icarus Verilog simulator build and run rules
 
#
 
#
 
.PHONY: $(ICARUS_SCRIPT)
 
.PHONY: $(ICARUS_SCRIPT)
Line 370... Line 373... 
                then echo "\`define END_INSNS "$$END_INSNS >> $@; \
 
                then echo "\`define END_INSNS "$$END_INSNS >> $@; \
 
        fi
 
        fi
 
        $(Q)if [ ! -z $$PRELOAD_RAM ]; \
 
        $(Q)if [ ! -z $$PRELOAD_RAM ]; \
 
                then echo "\`define PRELOAD_RAM "$$END_TIME >> $@; \
 
                then echo "\`define PRELOAD_RAM "$$END_TIME >> $@; \
 
        fi
 
        fi
 
        $(Q)if [ -z $$NO_SIM_LOGGING ]; \
 
        $(Q)if [ -z $$DISABLE_PROCESSOR_LOGS ]; \
 
                then echo "\`define OR1200_DISPLAY_ARCH_STATE" >> $@; \
 
                then echo "\`define PROCESSOR_MONITOR_ENABLE_LOGS" >> $@; \
 
        fi
 
        fi
 
        $(Q)if [ ! -z $$VPI ]; \
 
        $(Q)if [ ! -z $$VPI ]; \
 
                then echo "\`define VPI_DEBUG" >> $@; \
 
                then echo "\`define VPI_DEBUG" >> $@; \
 
        fi
 
        fi
 
        $(Q)if [ ! -z $$SIM_QUIET ]; \
 
        $(Q)if [ ! -z $$SIM_QUIET ]; \
Line 417... Line 420... 
.PHONY: $(TEST_SW_DIR)/$(TEST).vmem
 
.PHONY: $(TEST_SW_DIR)/$(TEST).vmem
 
$(TEST_SW_DIR)/$(TEST).vmem:
 
$(TEST_SW_DIR)/$(TEST).vmem:
 
        $(Q) echo; echo "\t### Compiling software ###"; echo;
 
        $(Q) echo; echo "\t### Compiling software ###"; echo;
 
        $(Q)$(MAKE) -C $(TEST_SW_DIR) $(TEST).vmem
 
        $(Q)$(MAKE) -C $(TEST_SW_DIR) $(TEST).vmem
 
 
 
 
 
 
 
# Rule to force generation of the processed orpsoc-defines.h file
 
 
 
processed-verilog-headers-in-c-for-vlt:
 
 
 
        $(Q)$(MAKE) -C $(SW_DIR)/lib processed-verilog-headers
 
 
 
# Now copy the file into the Verilated model build path
 
 
 
        $(Q)cp $(SW_DIR)/lib/include/orpsoc-defines.h $(SIM_VLT_DIR)
 
 
 
 
 
#
 
#
 
# Cleaning rules
 
# Cleaning rules
 
#
 
#
 
clean: clean-sim clean-sim-test-sw clean-bootrom clean-vlt clean-out clean-sw
 
clean: clean-sim clean-sim-test-sw clean-bootrom clean-vlt clean-out clean-sw
 
 
 
 
Line 566... Line 575... 
# Dummy files the RTL requires: timescale.v
 
# Dummy files the RTL requires: timescale.v
 
DUMMY_FILES_FOR_VLT=$(SIM_VLT_DIR)/timescale.v
 
DUMMY_FILES_FOR_VLT=$(SIM_VLT_DIR)/timescale.v
 
$(DUMMY_FILES_FOR_VLT):
 
$(DUMMY_FILES_FOR_VLT):
 
        $(Q)for file in $@; do if [ ! -e $$file ]; then touch $$file; fi; done
 
        $(Q)for file in $@; do if [ ! -e $$file ]; then touch $$file; fi; done
 
 
 
 
 
build-vlt: rtl $(SIM_VLT_DIR) $(DUMMY_FILES_FOR_VLT) $(VLT_MODEL_LINKS) $(SIM_VLT_DIR)/$(VLT_EXE)
 
build-vlt: rtl $(SIM_VLT_DIR) $(DUMMY_FILES_FOR_VLT) $(VLT_MODEL_LINKS) \
 
 
 
        processed-verilog-headers-in-c-for-vlt  $(SIM_VLT_DIR)/$(VLT_EXE)
 
 
 
 
 
# Main Cycle-accurate build rule
 
# Main Cycle-accurate build rule
 
prepare-vlt: build-vlt
 
prepare-vlt: build-vlt
 
        @echo;echo "\tCycle-accurate model compiled successfully"
 
        @echo;echo "\tCycle-accurate model compiled successfully"
 
        @echo;echo "\tRun the executable with the -h option for usage instructions:";echo
 
        @echo;echo "\tRun the executable with the -h option for usage instructions:";echo
Line 683... Line 693... 
        clean-vlt-after-profile-run \
 
        clean-vlt-after-profile-run \
 
        rtl $(SIM_VLT_DIR) $(DUMMY_FILES_FOR_VLT) $(VLT_MODEL_LINKS) \
 
        rtl $(SIM_VLT_DIR) $(DUMMY_FILES_FOR_VLT) $(VLT_MODEL_LINKS) \
 
        $(SIM_VLT_DIR)/$(VLT_EXE)
 
        $(SIM_VLT_DIR)/$(VLT_EXE)
 
 
 
 
 
$(SIM_VLT_DIR)/OrpsocMain.gcda: $(SIM_VLT_DIR)/$(VLT_EXE)-for-profiling
 
$(SIM_VLT_DIR)/OrpsocMain.gcda: $(SIM_VLT_DIR)/$(VLT_EXE)-for-profiling
 
        $(MAKE) -C $(SW_DIR)/dhry dhry.elf NUM_RUNS=5000
 
        $(MAKE) -C $(SW_DIR)/apps/dhry dhry.elf NUM_RUNS=5000
 
#       $(SIM_VLT_DIR)/$(VLT_EXE) -f $(SW_DIR)/dhry/dhry.elf -v -l sim.log --crash-monitor
 
#       $(SIM_VLT_DIR)/$(VLT_EXE) -f $(SW_DIR)/dhry/dhry.elf -v -l sim.log --crash-monitor
 
        $(SIM_VLT_DIR)/$(VLT_EXE) -f $(SW_DIR)/dhry/dhry.elf
 
        $(SIM_VLT_DIR)/$(VLT_EXE) -f $(SW_DIR)/apps/dhry/dhry.elf
 
 
 
 
 
# Clean all compiled things
 
# Clean all compiled things
 
clean-vlt-after-profile-run:
 
clean-vlt-after-profile-run:
 
        $(Q)echo "\tCleaning away compiled cycle-accurate files"
 
        $(Q)echo "\tCleaning away compiled cycle-accurate files"
 
        $(Q)rm -f $(SIM_VLT_DIR)/*.[oa] $(SIM_VLT_DIR)/$(VLT_EXE)
 
        $(Q)rm -f $(SIM_VLT_DIR)/*.[oa] $(SIM_VLT_DIR)/$(VLT_EXE)

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.