| Line 177... |
Line 177... |
#VOPT_ARGS=-voptargs="+acc=rnp"
|
#VOPT_ARGS=-voptargs="+acc=rnp"
|
VOPT_ARGS=+acc=rnpqv
|
VOPT_ARGS=+acc=rnpqv
|
endif
|
endif
|
# VSIM commands
|
# VSIM commands
|
# Suppressed warnings - 3009: Failed to open $readmemh() file
|
# Suppressed warnings - 3009: Failed to open $readmemh() file
|
# Suppressed warnings - 3009: Module 'blah' does not have a `timescale directive in effect, but previous modules do.
|
# Suppressed warnings - 3009: Module 'blah' does not have a `timescale
|
# Suppressed warnings - 8598: Non-positive replication multiplier inside concat. Replication will be ignored
|
# directive in effect, but previous modules do.
|
MGC_VSIM_ARGS= -suppress 7 -suppress 3009 -suppress 8598 -c $(QUIET) -do "set StdArithNoWarnings 1; run -all; exit"
|
# Suppressed warnings - 8598: Non-positive replication multiplier inside
|
|
# concat. Replication will be ignored
|
|
MGC_VSIM_ARGS= -suppress 7 -suppress 3009 -suppress 8598 -c $(QUIET) \
|
|
-do "set StdArithNoWarnings 1; run -all; exit"
|
# Options required when VPI option used
|
# Options required when VPI option used
|
ifeq ($(VPI), 1)
|
ifeq ($(VPI), 1)
|
MGC_VPI_LIB=$(VPI_SRC_C_DIR)/$(MODELTECH_VPILIB)
|
MGC_VPI_LIB=$(VPI_SRC_C_DIR)/$(MODELTECH_VPILIB)
|
MGC_VSIM_ARGS += -pli $(VPI_SRC_C_DIR)/$(MODELTECH_VPILIB)
|
MGC_VSIM_ARGS += -pli $(VPI_SRC_C_DIR)/$(MODELTECH_VPILIB)
|
|
|
| Line 204... |
Line 207... |
#
|
#
|
# Verilog DUT source variables
|
# Verilog DUT source variables
|
#
|
#
|
# A list of paths under rtl/verilog we wish to exclude for module searching
|
# A list of paths under rtl/verilog we wish to exclude for module searching
|
VERILOG_MODULES_EXCLUDE= include components
|
VERILOG_MODULES_EXCLUDE= include components
|
VERILOG_MODULES_EXCLUDE_LIST_E=$(shell for exclude in $(VERILOG_MODULES_EXCLUDE); do echo "-e $$exclude"; done)
|
VERILOG_MODULES_EXCLUDE_LIST_E=$(shell for exclude in \
|
RTL_VERILOG_MODULES=$(shell ls $(RTL_VERILOG_DIR) | grep -v $(VERILOG_MODULES_EXCLUDE_LIST_E) )
|
$(VERILOG_MODULES_EXCLUDE); do echo "-e $$exclude"; done)
|
|
RTL_VERILOG_MODULES=$(shell ls $(RTL_VERILOG_DIR) | grep -v \
|
|
$(VERILOG_MODULES_EXCLUDE_LIST_E) )
|
# Specific files to exclude, currently none.
|
# Specific files to exclude, currently none.
|
#VERILOG_EXCLUDE=
|
#VERILOG_EXCLUDE=
|
#VERILOG_EXCLUDE_LIST_E=$(shell for exclude in $(VERILOG_EXCLUDE); do echo "-e $$exclude"; done)
|
#VERILOG_EXCLUDE_LIST_E=$(shell for exclude in $(VERILOG_EXCLUDE); \
|
|
do echo "-e $$exclude"; done)
|
# List of verilog source files, minus excluded files
|
# List of verilog source files, minus excluded files
|
#RTL_VERILOG_SRC=$(shell for module in $(RTL_VERILOG_MODULES); do if [ -d $(RTL_VERILOG_DIR)/$$module ]; then ls $(RTL_VERILOG_DIR)/$$module/*.v | grep -v $(VERILOG_EXCLUDE_LIST_E); fi; done)
|
#RTL_VERILOG_SRC=$(shell for module in $(RTL_VERILOG_MODULES); do \
|
|
if [ -d $(RTL_VERILOG_DIR)/$$module ]; then \
|
|
ls $(RTL_VERILOG_DIR)/$$module/*.v | grep -v \
|
|
$(VERILOG_EXCLUDE_LIST_E); \
|
|
fi; done)
|
# List of verilog source files, ignoring excludes
|
# List of verilog source files, ignoring excludes
|
RTL_VERILOG_SRC=$(shell for module in $(RTL_VERILOG_MODULES); do if [ -d $(RTL_VERILOG_DIR)/$$module ]; then ls $(RTL_VERILOG_DIR)/$$module/*.v; fi; done)
|
RTL_VERILOG_SRC=$(shell for module in $(RTL_VERILOG_MODULES); do \
|
|
if [ -d $(RTL_VERILOG_DIR)/$$module ]; then \
|
|
ls $(RTL_VERILOG_DIR)/$$module/*.v; \
|
|
fi; done)
|
|
|
# List of verilog includes
|
# List of verilog includes
|
RTL_VERILOG_INCLUDES=$(shell ls $(RTL_VERILOG_INCLUDE_DIR)/*.*)
|
RTL_VERILOG_INCLUDES=$(shell ls $(RTL_VERILOG_INCLUDE_DIR)/*.*)
|
|
|
print-verilog-src:
|
print-verilog-src:
|
| Line 239... |
Line 252... |
# VHDL DUT source variables
|
# VHDL DUT source variables
|
#
|
#
|
# VHDL modules
|
# VHDL modules
|
#RTL_VHDL_MODULES=$(shell ls $(RTL_VHDL_DIR))
|
#RTL_VHDL_MODULES=$(shell ls $(RTL_VHDL_DIR))
|
# VHDL sources
|
# VHDL sources
|
#RTL_VHDL_SRC=$(shell for module in $(RTL_VHDL_MODULES); do if [ -d $(RTL_VHDL_DIR)/$$module ]; then ls $(RTL_VHDL_DIR)/$$module/*.vhd; fi; done)
|
#RTL_VHDL_SRC=$(shell for module in $(RTL_VHDL_MODULES); do \
|
|
if [ -d $(RTL_VHDL_DIR)/$$module ]; then \
|
|
ls $(RTL_VHDL_DIR)/$$module/*.vhd; \
|
|
fi; done)
|
#print-vhdl-src:
|
#print-vhdl-src:
|
# @echo echo; echo "\t### VHDL modules and source ###"; echo
|
# @echo echo; echo "\t### VHDL modules and source ###"; echo
|
# @echo "modules: "; echo $(RTL_VHDL_MODULES); echo
|
# @echo "modules: "; echo $(RTL_VHDL_MODULES); echo
|
# @echo "source: "$(RTL_VHDL_SRC)
|
# @echo "source: "$(RTL_VHDL_SRC)
|
|
|
|
|
# Testbench verilog source
|
# Testbench verilog source
|
BENCH_VERILOG_SRC=$(shell ls $(BENCH_VERILOG_DIR)/*.v | grep -v $(DESIGN_NAME)_testbench )
|
BENCH_VERILOG_SRC=$(shell ls $(BENCH_VERILOG_DIR)/*.v | grep -v \
|
|
$(DESIGN_NAME)_testbench )
|
|
|
print-bench-src:
|
print-bench-src:
|
$(Q)echo "\tBench verilog source"; \
|
$(Q)echo "\tBench verilog source"; \
|
echo $(BENCH_VERILOG_SRC)
|
echo $(BENCH_VERILOG_SRC)
|
|
|
# Testbench source subdirectory detection
|
# Testbench source subdirectory detection
|
BENCH_VERILOG_SRC_SUBDIRS +=$(shell for file in `ls $(BENCH_VERILOG_DIR)`; do if [ -d $(BENCH_VERILOG_DIR)/$$file ]; then echo $(BENCH_VERILOG_DIR)/$$file; fi; done)
|
BENCH_VERILOG_SRC_SUBDIRS +=$(shell for file in `ls $(BENCH_VERILOG_DIR)`; do \
|
|
if [ -d $(BENCH_VERILOG_DIR)/$$file ]; then \
|
|
echo $(BENCH_VERILOG_DIR)/$$file; \
|
|
fi; done)
|
|
|
# Compile script generation rules:
|
# Compile script generation rules:
|
|
|
modelsim_dut.scr: rtl $(RTL_VERILOG_SRC) $(RTL_VERILOG_INCLUDES) $(BOOTROM_VERILOG)
|
modelsim_dut.scr: rtl $(RTL_VERILOG_SRC) $(RTL_VERILOG_INCLUDES) \
|
|
$(BOOTROM_VERILOG)
|
$(Q)echo "+incdir+"$(RTL_VERILOG_INCLUDE_DIR) > $@;
|
$(Q)echo "+incdir+"$(RTL_VERILOG_INCLUDE_DIR) > $@;
|
$(Q)echo "+incdir+"$(RTL_SIM_SRC_DIR) >> $@;
|
$(Q)echo "+incdir+"$(RTL_SIM_SRC_DIR) >> $@;
|
$(Q)echo "+incdir+"$(BOOTROM_SW_DIR) >> $@;
|
$(Q)echo "+incdir+"$(BOOTROM_SW_DIR) >> $@;
|
$(Q)echo "+incdir+"$(BENCH_VERILOG_INCLUDE_DIR) >> $@;
|
$(Q)echo "+incdir+"$(BENCH_VERILOG_INCLUDE_DIR) >> $@;
|
$(Q)echo "+libext+.v" >> $@;
|
$(Q)echo "+libext+.v" >> $@;
|
$(Q)for module in $(RTL_VERILOG_MODULES); do if [ -d $(RTL_VERILOG_DIR)/$$module ]; then echo "-y " $(RTL_VERILOG_DIR)/$$module >> $@; fi; done
|
$(Q)for module in $(RTL_VERILOG_MODULES); do \
|
|
if [ -d $(RTL_VERILOG_DIR)/$$module ]; then \
|
|
echo "-y " $(RTL_VERILOG_DIR)/$$module >> $@; \
|
|
fi; done
|
$(Q)echo >> $@
|
$(Q)echo >> $@
|
|
|
modelsim_bench.scr: $(BENCH_VERILOG_SRC)
|
modelsim_bench.scr: $(BENCH_VERILOG_SRC)
|
$(Q)echo "+incdir+"$(BENCH_VERILOG_DIR) > $@;
|
$(Q)echo "+incdir+"$(BENCH_VERILOG_DIR) > $@;
|
$(Q)for path in $(BENCH_VERILOG_SRC_SUBDIRS); do echo "+incdir+"$$path >> $@; done
|
$(Q)for path in $(BENCH_VERILOG_SRC_SUBDIRS); do \
|
$(Q)for path in $(BENCH_VERILOG_SRC_SUBDIRS); do echo "-y "$$path >> $@; done
|
echo "+incdir+"$$path >> $@; \
|
|
done
|
|
$(Q)for path in $(BENCH_VERILOG_SRC_SUBDIRS); do \
|
|
echo "-y "$$path >> $@; \
|
|
done
|
$(Q)echo "+incdir+"$(RTL_VERILOG_INCLUDE_DIR) >> $@;
|
$(Q)echo "+incdir+"$(RTL_VERILOG_INCLUDE_DIR) >> $@;
|
$(Q)echo "+incdir+"$(RTL_SIM_SRC_DIR) >> $@;
|
$(Q)echo "+incdir+"$(RTL_SIM_SRC_DIR) >> $@;
|
$(Q)echo "+libext+.v" >> $@;
|
$(Q)echo "+libext+.v" >> $@;
|
$(Q)echo "-y" $(RTL_SIM_SRC_DIR) >> $@;
|
$(Q)echo "-y" $(RTL_SIM_SRC_DIR) >> $@;
|
$(Q)for vsrc in $(BENCH_VERILOG_SRC); do echo $$vsrc >> $@; done
|
$(Q)for vsrc in $(BENCH_VERILOG_SRC); do echo $$vsrc >> $@; done
|
| Line 299... |
Line 327... |
|
|
#
|
#
|
# Icarus Verilog simulator build and run rules
|
# Icarus Verilog simulator build and run rules
|
#
|
#
|
.PHONY: $(ICARUS_SCRIPT)
|
.PHONY: $(ICARUS_SCRIPT)
|
$(ICARUS_SCRIPT): $(RTL_VERILOG_SRC) $(RTL_VERILOG_INCLUDES) $(BOOTROM_VERILOG) $(BENCH_VERILOG_SRC)
|
$(ICARUS_SCRIPT): $(RTL_VERILOG_SRC) $(RTL_VERILOG_INCLUDES) \
|
|
$(BOOTROM_VERILOG) $(BENCH_VERILOG_SRC)
|
$(Q)echo "# Icarus Verilog simulation script" > $@
|
$(Q)echo "# Icarus Verilog simulation script" > $@
|
$(Q)echo "# Auto generated. Any alterations will be written over!" >> $@
|
$(Q)echo "# Auto generated. Any alterations will be written over!" >> $@
|
$(Q)echo "+incdir+"$(RTL_VERILOG_INCLUDE_DIR) > $@;
|
$(Q)echo "+incdir+"$(RTL_VERILOG_INCLUDE_DIR) > $@;
|
$(Q)echo "+incdir+"$(RTL_SIM_SRC_DIR) >> $@;
|
$(Q)echo "+incdir+"$(RTL_SIM_SRC_DIR) >> $@;
|
$(Q)echo "+incdir+"$(BENCH_VERILOG_DIR) >> $@;
|
$(Q)echo "+incdir+"$(BENCH_VERILOG_DIR) >> $@;
|
$(Q)echo "+incdir+"$(BOOTROM_SW_DIR) >> $@;
|
$(Q)echo "+incdir+"$(BOOTROM_SW_DIR) >> $@;
|
$(Q)for path in $(BENCH_VERILOG_SRC_SUBDIRS); do echo "+incdir+"$$path >> $@; done
|
$(Q)for path in $(BENCH_VERILOG_SRC_SUBDIRS); do \
|
$(Q)for path in $(BENCH_VERILOG_SRC_SUBDIRS); do echo "-y "$$path >> $@; done
|
echo "+incdir+"$$path >> $@; \
|
$(Q)for module in $(RTL_VERILOG_MODULES); do echo "-y " $(RTL_VERILOG_DIR)/$$module >> $@; done
|
done
|
|
$(Q)for path in $(BENCH_VERILOG_SRC_SUBDIRS); do \
|
|
echo "-y "$$path >> $@; \
|
|
done
|
|
$(Q)for module in $(RTL_VERILOG_MODULES); do \
|
|
echo "-y " $(RTL_VERILOG_DIR)/$$module >> $@; \
|
|
done
|
$(Q)echo "-y" $(RTL_SIM_SRC_DIR) >> $@;
|
$(Q)echo "-y" $(RTL_SIM_SRC_DIR) >> $@;
|
$(Q)echo "-y" $(BENCH_VERILOG_DIR) >> $@;
|
$(Q)echo "-y" $(BENCH_VERILOG_DIR) >> $@;
|
$(Q)echo $(BENCH_TOP) >> $@;
|
$(Q)echo $(BENCH_TOP) >> $@;
|
$(Q) echo >> $@
|
$(Q) echo >> $@
|
|
|
| Line 364... |
Line 399... |
$(Q)./$@
|
$(Q)./$@
|
|
|
# Include the test-defines.v generation rule
|
# Include the test-defines.v generation rule
|
include ../bin/definesgen.inc
|
include ../bin/definesgen.inc
|
|
|
# $(Q)for module in $(GATELEVEL_MODULES); do echo "\`define "$$module"_IS_GATELEVEL " >> $@; done
|
|
# More possible test defines go here
|
|
|
|
#
|
#
|
# Software make rules (called recursively)
|
# Software make rules (called recursively)
|
#
|
#
|
|
|
# Path for the current test
|
# Path for the current test
|
| Line 476... |
Line 508... |
$(Q)rm -rf $(RTL_SIM_RESULTS_DIR)/*.*
|
$(Q)rm -rf $(RTL_SIM_RESULTS_DIR)/*.*
|
|
|
# Clean away verilator build path and objects in SystemC path
|
# Clean away verilator build path and objects in SystemC path
|
clean-vlt:
|
clean-vlt:
|
$(Q)rm -rf $(SIM_VLT_DIR)
|
$(Q)rm -rf $(SIM_VLT_DIR)
|
$(Q)$(MAKE) -C $(BENCH_SYSC_SRC_DIR) -f $(BENCH_SYSC_SRC_DIR)/Modules.make clean
|
$(Q)$(MAKE) -C $(BENCH_SYSC_SRC_DIR) -f \
|
|
$(BENCH_SYSC_SRC_DIR)/Modules.make clean
|
|
|
clean-test-defines:
|
clean-test-defines:
|
$(Q)rm -f $(TEST_DEFINES_VLG)
|
$(Q)rm -f $(TEST_DEFINES_VLG)
|
|
|
clean-sim-test-sw:
|
clean-sim-test-sw:
|
| Line 509... |
Line 542... |
|
|
VLT_EXE=Vorpsoc_top
|
VLT_EXE=Vorpsoc_top
|
VLT_SCRIPT=verilator.scr
|
VLT_SCRIPT=verilator.scr
|
|
|
# Script for Verilator
|
# Script for Verilator
|
$(SIM_VLT_DIR)/$(VLT_SCRIPT): $(RTL_VERILOG_SRC) $(RTL_VERILOG_INCLUDES) $(BOOTROM_VERILOG)
|
$(SIM_VLT_DIR)/$(VLT_SCRIPT): $(RTL_VERILOG_SRC) $(RTL_VERILOG_INCLUDES) \
|
|
$(BOOTROM_VERILOG)
|
$(Q)echo "\tGenerating Verilator script"
|
$(Q)echo "\tGenerating Verilator script"
|
$(Q)echo "# Verilator sources script" > $@
|
$(Q)echo "# Verilator sources script" > $@
|
$(Q)echo "# Auto generated. Any alterations will be written over!" >> $@
|
$(Q)echo "# Auto generated. Any alterations will be written over!" >> $@
|
$(Q)echo "+incdir+"$(RTL_VERILOG_INCLUDE_DIR) > $@;
|
$(Q)echo "+incdir+"$(RTL_VERILOG_INCLUDE_DIR) > $@;
|
$(Q)echo "+incdir+"$(BOOTROM_SW_DIR) >> $@;
|
$(Q)echo "+incdir+"$(BOOTROM_SW_DIR) >> $@;
|
$(Q)echo "+incdir+"$(SIM_RUN_DIR) >> $@;
|
$(Q)echo "+incdir+"$(SIM_RUN_DIR) >> $@;
|
$(Q)for module in $(RTL_VERILOG_MODULES); do echo "-y " $(RTL_VERILOG_DIR)/$$module >> $@; done
|
$(Q)for module in $(RTL_VERILOG_MODULES); do \
|
|
echo "-y " $(RTL_VERILOG_DIR)/$$module >> $@; \
|
|
done
|
$(Q)echo $(DUT_TOP) >> $@;
|
$(Q)echo $(DUT_TOP) >> $@;
|
$(Q) echo >> $@
|
$(Q) echo >> $@
|
|
|
|
|
SYSC_LIB_ARCH_DIR=$(shell ls $$SYSTEMC | grep "lib-")
|
SYSC_LIB_ARCH_DIR=$(shell ls $$SYSTEMC | grep "lib-")
|
| Line 556... |
Line 592... |
# If set on the command line we build the cycle accurate model which will
|
# If set on the command line we build the cycle accurate model which will
|
# generate verilator-specific profiling information. This is useful for
|
# generate verilator-specific profiling information. This is useful for
|
# checking the efficiency of the model - not really useful for checking code
|
# checking the efficiency of the model - not really useful for checking code
|
# or the function of the model.
|
# or the function of the model.
|
ifdef VLT_DO_PERFORMANCE_PROFILE_BUILD
|
ifdef VLT_DO_PERFORMANCE_PROFILE_BUILD
|
VLT_CPPFLAGS += -fprofile-generate -fbranch-probabilities -fvpt -funroll-loops -fpeel-loops -ftracer
|
VLT_CPPFLAGS += -fprofile-generate -fbranch-probabilities -fvpt \
|
|
-funroll-loops -fpeel-loops -ftracer
|
else
|
else
|
VLT_CPPFLAGS +=-fprofile-use -Wcoverage-mismatch
|
VLT_CPPFLAGS +=-fprofile-use -Wcoverage-mismatch
|
endif
|
endif
|
|
|
# Set VLT_IN_GDB=1 when making if going to run the cycle accurate model
|
# Set VLT_IN_GDB=1 when making if going to run the cycle accurate model
|
| Line 579... |
Line 616... |
# Verilator tuning
|
# Verilator tuning
|
# Inlining:
|
# Inlining:
|
VLT_FLAGS +=--inline-mult 1
|
VLT_FLAGS +=--inline-mult 1
|
# Optimisation option for Verilator scripts
|
# Optimisation option for Verilator scripts
|
VLT_FLAGS +=-O3
|
VLT_FLAGS +=-O3
|
# X-assign - at reset, all signals are set to random values, helps find rst bugs
|
# X-assign - at reset, all signals are set to random values, helps find
|
|
# reset bugs
|
VLT_FLAGS +=-x-assign unique
|
VLT_FLAGS +=-x-assign unique
|
|
|
VLT_TRACEOBJ = verilated_vcd_c
|
VLT_TRACEOBJ = verilated_vcd_c
|
|
|
|
|
| Line 593... |
Line 631... |
|
|
# List of sources for rule sensitivity
|
# List of sources for rule sensitivity
|
SYSC_MODEL_SOURCES=$(shell ls $(BENCH_SYSC_SRC_DIR)/*.cpp)
|
SYSC_MODEL_SOURCES=$(shell ls $(BENCH_SYSC_SRC_DIR)/*.cpp)
|
SYSC_MODEL_SOURCES +=$(shell ls $(BENCH_SYSC_INCLUDE_DIR)/*.h)
|
SYSC_MODEL_SOURCES +=$(shell ls $(BENCH_SYSC_INCLUDE_DIR)/*.h)
|
|
|
VLT_MODULES_OBJS=$(shell for mod in $(SYSC_MODELS_BUILD); do echo $(SIM_VLT_DIR)/$$mod.o; done)
|
VLT_MODULES_OBJS=$(shell for mod in $(SYSC_MODELS_BUILD); do \
|
|
echo $(SIM_VLT_DIR)/$$mod.o; \
|
VLT_MODEL_LINKS=$(shell for SYSCMODEL in $(SYSC_MODELS); do echo $(SIM_VLT_DIR)/$$SYSCMODEL.cpp; done)
|
done)
|
|
|
|
VLT_MODEL_LINKS=$(shell for SYSCMODEL in $(SYSC_MODELS); do \
|
|
echo $(SIM_VLT_DIR)/$$SYSCMODEL.cpp; \
|
|
done)
|
|
|
# Make Verilator build path if it doesn't exist
|
# Make Verilator build path if it doesn't exist
|
$(SIM_VLT_DIR):
|
$(SIM_VLT_DIR):
|
mkdir -p $@
|
mkdir -p $@
|
|
|
| Line 616... |
Line 658... |
@echo;echo "\tCycle-accurate model compiled successfully"
|
@echo;echo "\tCycle-accurate model compiled successfully"
|
@echo;echo "\tRun the executable with the -h option for usage instructions:";echo
|
@echo;echo "\tRun the executable with the -h option for usage instructions:";echo
|
$(SIM_VLT_DIR)/$(VLT_EXE) -h
|
$(SIM_VLT_DIR)/$(VLT_EXE) -h
|
@echo;echo
|
@echo;echo
|
|
|
$(SIM_VLT_DIR)/$(VLT_EXE): $(SIM_VLT_DIR)/lib$(VLT_EXE).a $(SIM_VLT_DIR)/OrpsocMain.o
|
$(SIM_VLT_DIR)/$(VLT_EXE): $(SIM_VLT_DIR)/lib$(VLT_EXE).a \
|
# Final linking of the simulation executable. Order of libraries here is important!
|
$(SIM_VLT_DIR)/OrpsocMain.o
|
|
# Final linking of the simulation executable. Order of libraries here is
|
|
# important!
|
$(Q)echo; echo "\tGenerating simulation executable"; echo
|
$(Q)echo; echo "\tGenerating simulation executable"; echo
|
$(Q)cd $(SIM_VLT_DIR) && g++ $(VLT_DEBUG_COMPILE_FLAGS) $(VLT_CPPFLAGS) -I$(BENCH_SYSC_INCLUDE_DIR) -I$(SIM_VLT_DIR) -I$(VERILATOR_ROOT)/include -I$(SYSTEMC)/include -o $(VLT_EXE) -L. -L$(BENCH_SYSC_SRC_DIR) -L$(SYSTEMC)/$(SYSC_LIB_ARCH_DIR) OrpsocMain.o -l$(VLT_EXE) -lmodules -lsystemc
|
$(Q)cd $(SIM_VLT_DIR) && \
|
|
g++ $(VLT_DEBUG_COMPILE_FLAGS) \
|
|
$(VLT_CPPFLAGS) -I$(BENCH_SYSC_INCLUDE_DIR) -I$(SIM_VLT_DIR) \
|
|
-I$(VERILATOR_ROOT)/include -I$(SYSTEMC)/include -o $(VLT_EXE) \
|
|
-L. -L$(BENCH_SYSC_SRC_DIR) -L$(SYSTEMC)/$(SYSC_LIB_ARCH_DIR) \
|
|
OrpsocMain.o -l$(VLT_EXE) -lmodules -lsystemc
|
|
|
# Now compile the top level systemC "testbench" module from the systemC source path
|
# Now compile the top level systemC "testbench" module from the systemC source
|
|
# path
|
$(SIM_VLT_DIR)/OrpsocMain.o: $(BENCH_SYSC_SRC_DIR)/OrpsocMain.cpp
|
$(SIM_VLT_DIR)/OrpsocMain.o: $(BENCH_SYSC_SRC_DIR)/OrpsocMain.cpp
|
@echo; echo "\tCompiling top level SystemC testbench"; echo
|
@echo; echo "\tCompiling top level SystemC testbench"; echo
|
cd $(SIM_VLT_DIR) && g++ $(VLT_DEBUG_COMPILE_FLAGS) $(VLT_CPPFLAGS) $(TRACE_FLAGS) -I$(BENCH_SYSC_INCLUDE_DIR) -I$(SIM_VLT_DIR) -I$(VERILATOR_ROOT)/include -I$(SYSTEMC)/include -c $(BENCH_SYSC_SRC_DIR)/OrpsocMain.cpp
|
cd $(SIM_VLT_DIR) && \
|
|
g++ $(VLT_DEBUG_COMPILE_FLAGS) $(VLT_CPPFLAGS) $(TRACE_FLAGS) \
|
$(SIM_VLT_DIR)/lib$(VLT_EXE).a: $(SIM_VLT_DIR)/$(VLT_EXE)__ALL.a $(VLT_MODULES_OBJS) $(SIM_VLT_DIR)/verilated.o
|
-I$(BENCH_SYSC_INCLUDE_DIR) -I$(SIM_VLT_DIR) \
|
# Now archive all of the libraries from verilator witht he other modules we might have
|
-I$(VERILATOR_ROOT)/include -I$(SYSTEMC)/include -c \
|
|
$(BENCH_SYSC_SRC_DIR)/OrpsocMain.cpp
|
|
|
|
$(SIM_VLT_DIR)/lib$(VLT_EXE).a: $(SIM_VLT_DIR)/$(VLT_EXE)__ALL.a \
|
|
$(VLT_MODULES_OBJS) $(SIM_VLT_DIR)/verilated.o
|
|
# Now archive all of the libraries from verilator witht he other modules we
|
|
# might have
|
@echo; echo "\tArchiving libraries into lib"$(VLT_EXE)".a"; echo
|
@echo; echo "\tArchiving libraries into lib"$(VLT_EXE)".a"; echo
|
$(Q)cd $(SIM_VLT_DIR) && \
|
$(Q)cd $(SIM_VLT_DIR) && \
|
cp $(VLT_EXE)__ALL.a lib$(VLT_EXE).a && \
|
cp $(VLT_EXE)__ALL.a lib$(VLT_EXE).a && \
|
ar rcs lib$(VLT_EXE).a verilated.o; \
|
ar rcs lib$(VLT_EXE).a verilated.o; \
|
for SYSCMODEL in $(SYSC_MODELS_BUILD); do \
|
for SYSCMODEL in $(SYSC_MODELS_BUILD); do \
|
| Line 659... |
Line 715... |
export USER_CPPFLAGS="$(VLT_CPPFLAGS) -I$(BENCH_SYSC_INCLUDE_DIR)"; \
|
export USER_CPPFLAGS="$(VLT_CPPFLAGS) -I$(BENCH_SYSC_INCLUDE_DIR)"; \
|
export USER_LDDFLAGS="$(VLT_CPPFLAGS)"; \
|
export USER_LDDFLAGS="$(VLT_CPPFLAGS)"; \
|
$(MAKE) -f $(VLT_EXE).mk $$SYSCMODEL.o; \
|
$(MAKE) -f $(VLT_EXE).mk $$SYSCMODEL.o; \
|
done
|
done
|
|
|
$(SIM_VLT_DIR)/$(VLT_EXE)__ALL.a: $(SIM_VLT_DIR)/$(VLT_EXE).mk $(SYSC_MODEL_SOURCES)
|
$(SIM_VLT_DIR)/$(VLT_EXE)__ALL.a: $(SIM_VLT_DIR)/$(VLT_EXE).mk \
|
|
$(SYSC_MODEL_SOURCES)
|
@echo; echo "\tCompiling main design"; echo
|
@echo; echo "\tCompiling main design"; echo
|
$(Q)cd $(SIM_VLT_DIR) && \
|
$(Q)cd $(SIM_VLT_DIR) && \
|
export USER_CPPFLAGS="$(VLT_CPPFLAGS)"; \
|
export USER_CPPFLAGS="$(VLT_CPPFLAGS)"; \
|
export USER_LDDFLAGS="$(VLT_CPPFLAGS)"; \
|
export USER_LDDFLAGS="$(VLT_CPPFLAGS)"; \
|
$(MAKE) -f $(VLT_EXE).mk $(VLT_EXE)__ALL.a
|
$(MAKE) -f $(VLT_EXE).mk $(VLT_EXE)__ALL.a
|
|
|
$(SIM_VLT_DIR)/$(VLT_EXE).mk: $(SIM_VLT_DIR)/$(VLT_SCRIPT) $(BENCH_SYSC_SRC_DIR)/libmodules.a
|
$(SIM_VLT_DIR)/$(VLT_EXE).mk: $(SIM_VLT_DIR)/$(VLT_SCRIPT) \
|
|
$(BENCH_SYSC_SRC_DIR)/libmodules.a
|
# Now call verilator to generate the .mk files
|
# Now call verilator to generate the .mk files
|
$(Q)echo; echo "\tGenerating makefiles with Verilator"; echo
|
$(Q)echo; echo "\tGenerating makefiles with Verilator"; echo
|
$(Q)cd $(SIM_VLT_DIR) && \
|
$(Q)cd $(SIM_VLT_DIR) && \
|
verilator -language 1364-2001 --top-module orpsoc_top -Mdir . -sc $(VLT_FLAGS) -I$(BENCH_SYSC_INCLUDE_DIR) -I$(BENCH_SYSC_SRC_DIR) -f $(SIM_VLT_DIR)/$(VLT_SCRIPT)
|
verilator -language 1364-2001 --top-module orpsoc_top -Mdir . -sc \
|
|
$(VLT_FLAGS) -I$(BENCH_SYSC_INCLUDE_DIR) -I$(BENCH_SYSC_SRC_DIR) \
|
|
-f $(SIM_VLT_DIR)/$(VLT_SCRIPT)
|
|
|
# SystemC modules library
|
# SystemC modules library
|
$(BENCH_SYSC_SRC_DIR)/libmodules.a:
|
$(BENCH_SYSC_SRC_DIR)/libmodules.a:
|
@echo; echo "\tCompiling SystemC modules"; echo
|
@echo; echo "\tCompiling SystemC modules"; echo
|
$(Q)export VLT_CPPFLAGS="$(VLT_CPPFLAGS)"; \
|
$(Q)export VLT_CPPFLAGS="$(VLT_CPPFLAGS)"; \
|
$(MAKE) -C $(BENCH_SYSC_SRC_DIR) -f $(BENCH_SYSC_SRC_DIR)/Modules.make $(VLT_SYSC_DEBUG_DEFINE)
|
$(MAKE) -C $(BENCH_SYSC_SRC_DIR) \
|
|
-f $(BENCH_SYSC_SRC_DIR)/Modules.make $(VLT_SYSC_DEBUG_DEFINE)
|
|
|
print-vlt-model-link-paths:
|
print-vlt-model-link-paths:
|
$(Q)echo $(VLT_MODEL_LINKS)
|
$(Q)echo $(VLT_MODEL_LINKS)
|
|
|
$(VLT_MODEL_LINKS):
|
$(VLT_MODEL_LINKS):
|
# Link all the required system C model files into the verilator work dir
|
# Link all the required system C model files into the verilator work dir
|
for SYSCMODEL in $(SYSC_MODELS); do \
|
for SYSCMODEL in $(SYSC_MODELS); do \
|
if [ ! -e $(SIM_VLT_DIR)/$$SYSCMODEL.cpp ]; then \
|
if [ ! -e $(SIM_VLT_DIR)/$$SYSCMODEL.cpp ]; then \
|
echo "\tLinking SystemC model $$SYSCMODEL Verilator model build path"; \
|
echo "\tLinking SystemC model $$SYSCMODEL Verilator model build path"; \
|
ln -s $(BENCH_SYSC_SRC_DIR)/$$SYSCMODEL.cpp $(SIM_VLT_DIR)/$$SYSCMODEL.cpp; \
|
ln -s $(BENCH_SYSC_SRC_DIR)/$$SYSCMODEL.cpp \
|
ln -s $(BENCH_SYSC_INCLUDE_DIR)/$$SYSCMODEL.h $(SIM_VLT_DIR)/$$SYSCMODEL.h; \
|
$(SIM_VLT_DIR)/$$SYSCMODEL.cpp; \
|
|
ln -s $(BENCH_SYSC_INCLUDE_DIR)/$$SYSCMODEL.h \
|
|
$(SIM_VLT_DIR)/$$SYSCMODEL.h; \
|
fi; \
|
fi; \
|
done
|
done
|
|
|
|
|
################################################################################
|
################################################################################
|
| Line 725... |
Line 788... |
rtl $(SIM_VLT_DIR) $(DUMMY_FILES_FOR_VLT) $(VLT_MODEL_LINKS) \
|
rtl $(SIM_VLT_DIR) $(DUMMY_FILES_FOR_VLT) $(VLT_MODEL_LINKS) \
|
$(SIM_VLT_DIR)/$(VLT_EXE)
|
$(SIM_VLT_DIR)/$(VLT_EXE)
|
|
|
$(SIM_VLT_DIR)/OrpsocMain.gcda: $(SIM_VLT_DIR)/$(VLT_EXE)-for-profiling
|
$(SIM_VLT_DIR)/OrpsocMain.gcda: $(SIM_VLT_DIR)/$(VLT_EXE)-for-profiling
|
$(MAKE) -C $(SW_DIR)/apps/dhry dhry.elf NUM_RUNS=5000
|
$(MAKE) -C $(SW_DIR)/apps/dhry dhry.elf NUM_RUNS=5000
|
# $(SIM_VLT_DIR)/$(VLT_EXE) -f $(SW_DIR)/dhry/dhry.elf -v -l sim.log --crash-monitor
|
|
$(SIM_VLT_DIR)/$(VLT_EXE) -f $(SW_DIR)/apps/dhry/dhry.elf
|
$(SIM_VLT_DIR)/$(VLT_EXE) -f $(SW_DIR)/apps/dhry/dhry.elf
|
|
|
# Clean all compiled things
|
# Clean all compiled things
|
clean-vlt-after-profile-run:
|
clean-vlt-after-profile-run:
|
$(Q)echo "\tCleaning away compiled cycle-accurate files"
|
$(Q)echo "\tCleaning away compiled cycle-accurate files"
|
| Line 749... |
Line 811... |
|
|
|
|
lint-vlt: $(SIM_VLT_DIR) rtl $(DUMMY_FILES_FOR_VLT) $(SIM_VLT_DIR)/$(VLT_SCRIPT)
|
lint-vlt: $(SIM_VLT_DIR) rtl $(DUMMY_FILES_FOR_VLT) $(SIM_VLT_DIR)/$(VLT_SCRIPT)
|
$(Q)echo; echo "\tLinting design with Verilator"; echo
|
$(Q)echo; echo "\tLinting design with Verilator"; echo
|
$(Q)cd $(SIM_VLT_DIR) && \
|
$(Q)cd $(SIM_VLT_DIR) && \
|
verilator -language 1364-2001 --top-module orpsoc_top --lint-only -Mdir . -sc $(VLT_FLAGS) -I$(BENCH_SYSC_INCLUDE_DIR) -I$(BENCH_SYSC_SRC_DIR) -f $(SIM_VLT_DIR)/$(VLT_SCRIPT)
|
verilator -language 1364-2001 --top-module orpsoc_top --lint-only \
|
|
-Mdir . -sc $(VLT_FLAGS) -I$(BENCH_SYSC_INCLUDE_DIR) \
|
|
-I$(BENCH_SYSC_SRC_DIR) -f $(SIM_VLT_DIR)/$(VLT_SCRIPT)
|
|
|
################################################################################
|
################################################################################
|
# Architectural simulator test rules
|
# Architectural simulator test rules
|
################################################################################
|
################################################################################
|
|
|
ARCH_SIM_EXE ?=or32-elf-sim
|
ARCH_SIM_EXE ?=or32-elf-sim
|
ARCH_SIM_CFG ?= ../bin/or1ksim-orpsocv2.cfg
|
ARCH_SIM_CFG ?= ../bin/refdesign-or1ksim.cfg
|
ARCH_SIM_OPTS ?= -q
|
ARCH_SIM_OPTS ?= -q
|
|
|
.PHONY: rtl-test
|
.PHONY: rtl-test
|
sim-test: clean-sim-test-sw sw-elf
|
sim-test: clean-sim-test-sw sw-elf
|
$(Q)echo; echo "\t### Launching simulation ###"; echo
|
$(Q)echo; echo "\t### Launching simulation ###"; echo
|
