OpenCores

Line 266...

MGC_COMMAND_FILE=modelsim.scr

MGC_COMMAND_FILE=modelsim.scr

ARCH_SIM_EXE=or32-elf-sim

ARCH_SIM_EXE=or32-elf-sim

ARCH_SIM_CFG_FILE=or1ksim-orpsocv2.cfg

ARCH_SIM_CFG_FILE=or1ksim-orpsocv2.cfg

# Set V=1 when calling make to enable verbose output

# mainly for debugging purposes.

ifeq ($(V), 1)

Q=

else

Q=@

endif

# If USE_SDRAM is defined we'll add it to the simulator's defines on the

# If USE_SDRAM is defined we'll add it to the simulator's defines on the

# command line becuase it's used by many different modules and it's easier

# command line becuase it's used by many different modules and it's easier

# to do it this way than make them all include a file.

# to do it this way than make them all include a file.

ifdef USE_SDRAM

ifdef USE_SDRAM

EVENT_SIM_FLAGS += "-D USE_SDRAM=$(USE_SDRAM)"

EVENT_SIM_FLAGS += "-D USE_SDRAM=$(USE_SDRAM)"

Line 339...

Line 347...

################################################################################

################################################################################

$(RTL_VERILOG_DIR)/components/wb_sdram_ctrl/wb_sdram_ctrl_fsm.v:

$(RTL_VERILOG_DIR)/components/wb_sdram_ctrl/wb_sdram_ctrl_fsm.v:

        @cd $(RTL_VERILOG_DIR)/components/wb_sdram_ctrl && perl fizzim.pl -encoding onehot -terse < wb_sdram_ctrl_fsm.fzm > wb_sdram_ctrl_fsm.v

        @cd $(RTL_VERILOG_DIR)/components/wb_sdram_ctrl && perl fizzim.pl -encoding onehot -terse < wb_sdram_ctrl_fsm.fzm > wb_sdram_ctrl_fsm.v

.PHONY: prepare_rtl

.PHONY: prepare-rtl

prepare_rtl: $(RTL_VERILOG_DIR)/components/wb_sdram_ctrl/wb_sdram_ctrl_fsm.v

prepare-rtl: $(RTL_VERILOG_DIR)/components/wb_sdram_ctrl/wb_sdram_ctrl_fsm.v

$(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE): $(SIM_BIN_DIR)/$(SIM_COMMANDFILE)

$(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE): $(SIM_BIN_DIR)/$(SIM_COMMANDFILE)

        @sed < $(SIM_BIN_DIR)/$(SIM_COMMANDFILE) > $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE) \

        $(Q)sed < $(SIM_BIN_DIR)/$(SIM_COMMANDFILE) > $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE) \

                -e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)!              \

                -e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)!              \

                -e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)!                  \

                -e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)!                  \

                -e s!\$$BACKEND_DIR!$(BACKEND_DIR)!                  \

                -e s!\$$BACKEND_DIR!$(BACKEND_DIR)!                  \

                -e \\!^//.*\$$!d -e \\!^\$$!d ; \

                -e \\!^//.*\$$!d -e \\!^\$$!d ; \

        echo "+define+TEST_DEFINE_FILE=\"test_define.v\"" >> $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE); \

        echo "+define+TEST_DEFINE_FILE=\"test_define.v\"" >> $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE); \

Line 360...

Line 368...

ifdef UART_PRINTF

ifdef UART_PRINTF

TEST_SW_MAKE_OPTS="UART_PRINTF=1"

TEST_SW_MAKE_OPTS="UART_PRINTF=1"

endif

endif

.PHONY: prepare_sw

.PHONY: prepare-sw

prepare_sw:

prepare-sw:

        @$(MAKE) -C $(SW_DIR)/support all $(TEST_SW_MAKE_OPTS)

        $(Q)$(MAKE) -C $(SW_DIR)/support all $(TEST_SW_MAKE_OPTS)

        @$(MAKE) -C $(SW_DIR)/utils all

        $(Q)$(MAKE) -C $(SW_DIR)/utils all

# A rule with UART_PRINTF hard defined ... used by verilator make sw

# A rule with UART_PRINTF hard defined ... used by verilator make sw

prepare_sw_uart_printf:

prepare-sw-uart-printf:

        @$(MAKE) -C $(SW_DIR)/support all UART_PRINTF=1 $(TEST_SW_MAKE_OPTS)

        $(Q)$(MAKE) -C $(SW_DIR)/support all UART_PRINTF=1 $(TEST_SW_MAKE_OPTS)

        @$(MAKE) -C $(SW_DIR)/utils all

        $(Q)$(MAKE) -C $(SW_DIR)/utils all

prepare_dirs:

prepare-dirs:

        @if [ ! -d $(SIM_RESULTS_DIR) ]; then mkdir -p $(SIM_RESULTS_DIR); fi

        $(Q)if [ ! -d $(SIM_RESULTS_DIR) ]; then mkdir -p $(SIM_RESULTS_DIR); fi

# Rough guide to how event driven simulation test loop works:

# Rough guide to how event driven simulation test loop works:

# 1. Compile software support programs.

# 1. Compile software support programs.

Line 416...

Line 424...

#               printf() calls.

#               printf() calls.

#       NO_SIM_LOGGING=1

#       NO_SIM_LOGGING=1

#               Turn off generation of logging files in the ../results

#               Turn off generation of logging files in the ../results

#               directory.

#               directory.

rtl-tests: $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE) prepare_sw prepare_rtl prepare_dirs

rtl-tests: $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE) prepare-sw prepare-rtl prepare-dirs

        @echo

        @echo

        @echo "Beginning loop that will complete the following tests: $(TESTS)"

        @echo "Beginning loop that will complete the following tests: $(TESTS)"

        @echo

        @echo

        @for TEST in $(TESTS); do \

        $(Q)for TEST in $(TESTS); do \

                echo "################################################################################"; \

                echo "################################################################################"; \

                echo; \

                echo; \

                echo "\t#### Current test: $$TEST ####"; echo; \

                echo "\t#### Current test: $$TEST ####"; echo; \

                echo "\t#### Compiling software ####"; echo; \

                echo "\t#### Compiling software ####"; echo; \

                CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \

                CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \

Line 467...

Line 475...

        echo "Test results: "$$TESTS_PASSED" out of "$$TESTS_PERFORMED" tests passed"; echo

        echo "Test results: "$$TESTS_PASSED" out of "$$TESTS_PERFORMED" tests passed"; echo

# Use NCSIM instead of icarus

# Use NCSIM instead of icarus

rtl-nc-tests: prepare_sw prepare_rtl prepare_dirs

rtl-nc-tests: prepare-sw prepare-rtl prepare-dirs

        @echo

        @echo

        @echo "Beginning loop that will complete the following tests: $(TESTS)"

        @echo "Beginning loop that will complete the following tests: $(TESTS)"

        @echo

        @echo

        @for TEST in $(TESTS); do \

        $(Q)for TEST in $(TESTS); do \

                echo "################################################################################"; \

                echo "################################################################################"; \

                echo; \

                echo; \

                echo "\t#### Current test: $$TEST ####"; echo; \

                echo "\t#### Current test: $$TEST ####"; echo; \

                echo "\t#### Compiling software ####"; echo; \

                echo "\t#### Compiling software ####"; echo; \

                CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \

                CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \

Line 538...

Line 546...

VPI_VERILOG_DIR=$(VPI_DIR)/verilog

VPI_VERILOG_DIR=$(VPI_DIR)/verilog

VPI_LIB_NAME=jp_vpi

VPI_LIB_NAME=jp_vpi

ICARUS_VPI_OPTS=-M$(VPI_C_DIR) -m$(VPI_LIB_NAME)

ICARUS_VPI_OPTS=-M$(VPI_C_DIR) -m$(VPI_LIB_NAME)

VPI_TEST_SW ?= dhry-nocache-O2

VPI_TEST_SW ?= dhry-nocache-O2

prepare_vpi:

prepare-vpi:

## Build the VPI library

## Build the VPI library

        $(MAKE) -C $(VPI_C_DIR) $(VPI_LIB_NAME)

        $(MAKE) -C $(VPI_C_DIR) $(VPI_LIB_NAME)

clean-vpi:

clean-vpi:

        $(MAKE) -C $(VPI_C_DIR) clean

        $(MAKE) -C $(VPI_C_DIR) clean

rtl-debug: prepare_sw_uart_printf prepare_rtl prepare_vpi prepare_dirs

rtl-debug: prepare-sw-uart-printf prepare-rtl prepare-vpi prepare-dirs

## Prepare the software for the test

## Prepare the software for the test

        @echo "\t#### Compiling software ####"; echo; \

        @echo "\t#### Compiling software ####"; echo; \

        CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $(VPI_TEST_SW) | cut -d "-" -f 1`; \

        CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $(VPI_TEST_SW) | cut -d "-" -f 1`; \

        $(MAKE) -C $$CURRENT_TEST_SW_DIR $(VPI_TEST_SW) $(TEST_SW_MAKE_OPTS); \

        $(MAKE) -C $$CURRENT_TEST_SW_DIR $(VPI_TEST_SW) $(TEST_SW_MAKE_OPTS); \

        rm -f $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \

        rm -f $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \

        rm -f $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \

        rm -f $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \

        ln -s $$CURRENT_TEST_SW_DIR/$(VPI_TEST_SW)$(FLASH_MEM_FILE_SUFFIX) $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \

        ln -s $$CURRENT_TEST_SW_DIR/$(VPI_TEST_SW)$(FLASH_MEM_FILE_SUFFIX) $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \

        ln -s $$CURRENT_TEST_SW_DIR/$(VPI_TEST_SW).vmem $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE)

        ln -s $$CURRENT_TEST_SW_DIR/$(VPI_TEST_SW).vmem $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE)

## Generate the icarus script we'll compile with

## Generate the icarus script we'll compile with

        @sed < $(SIM_BIN_DIR)/$(ICARUS_COMMAND_FILE) > $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated \

        $(Q)sed < $(SIM_BIN_DIR)/$(ICARUS_COMMAND_FILE) > $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated \

                -e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)!              \

                -e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)!              \

                -e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)!                  \

                -e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)!                  \

                -e s!\$$BACKEND_DIR!$(BACKEND_DIR)!                  \

                -e s!\$$BACKEND_DIR!$(BACKEND_DIR)!                  \

                -e \\!^//.*\$$!d -e \\!^\$$!d

                -e \\!^//.*\$$!d -e \\!^\$$!d

## Add a couple of extra defines to the icarus compile script

## Add a couple of extra defines to the icarus compile script

        @echo "+define+TEST_DEFINE_FILE=\"test_define.v\"" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated

        $(Q)echo "+define+TEST_DEFINE_FILE=\"test_define.v\"" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated

## The define that enables the VPI debug module

## The define that enables the VPI debug module

        @echo "+define+VPI_DEBUG_ENABLE" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated

        $(Q)echo "+define+VPI_DEBUG_ENABLE" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated

        @if [ ! -z $$VCD ];then echo "+define+VCD" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated;fi

        $(Q)if [ ! -z $$VCD ];then echo "+define+VCD" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated;fi

## Unless NO_UART_PRINTF=1 we use printf via the UART

## Unless NO_UART_PRINTF=1 we use printf via the UART

        @if [ -z $$NO_UART_PRINTF ];then echo "+define+UART_PRINTF" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; fi

        $(Q)if [ -z $$NO_UART_PRINTF ];then echo "+define+UART_PRINTF" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; fi

        @echo "\`define TEST_NAME_STRING \"$(VPI_TEST_SW)-vpi\"" > $(SIM_RUN_DIR)/test_define.v

        $(Q)echo "\`define TEST_NAME_STRING \"$(VPI_TEST_SW)-vpi\"" > $(SIM_RUN_DIR)/test_define.v

        @echo "\`define TEST_RESULTS_DIR \"$(SIM_RESULTS_DIR)/\" " >> $(SIM_RUN_DIR)/test_define.v

        $(Q)echo "\`define TEST_RESULTS_DIR \"$(SIM_RESULTS_DIR)/\" " >> $(SIM_RUN_DIR)/test_define.v

        @if [ -z $$NO_SIM_LOGGING ]; then echo "\`define OR1200_DISPLAY_ARCH_STATE" >> $(SIM_RUN_DIR)/test_define.v; fi

        $(Q)if [ -z $$NO_SIM_LOGGING ]; then echo "\`define OR1200_DISPLAY_ARCH_STATE" >> $(SIM_RUN_DIR)/test_define.v; fi

        @echo

        @echo

        @echo "\t#### Compiling RTL ####"

        @echo "\t#### Compiling RTL ####"

        @rm -f $(SIM_RUN_DIR)/a.out

        $(Q)rm -f $(SIM_RUN_DIR)/a.out

        @$(ICARUS) -sorpsoc_testbench -c $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated $(EVENT_SIM_FLAGS)

        $(Q)$(ICARUS) -sorpsoc_testbench -c $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated $(EVENT_SIM_FLAGS)

        @echo

        @echo

        @echo "\t#### Beginning simulation with VPI debug module enabled ####"; echo

        @echo "\t#### Beginning simulation with VPI debug module enabled ####"; echo

        @$(ICARUS_VVP) $(ICARUS_VPI_OPTS) -l $(SIM_RESULTS_DIR)/$(VPI_TEST_SW)-vvp-out.log a.out

        $(Q)$(ICARUS_VVP) $(ICARUS_VPI_OPTS) -l $(SIM_RESULTS_DIR)/$(VPI_TEST_SW)-vvp-out.log a.out

################################################################################

################################################################################

# Verilator model build rules

# Verilator model build rules

################################################################################

################################################################################

Line 626...

Line 634...

# This is the list of extra models we'll issue make commands for

# This is the list of extra models we'll issue make commands for

# Included is the SystemPerl trace model

# Included is the SystemPerl trace model

SYSC_MODELS_BUILD=$(SYSC_MODELS) $(VLT_TRACEOBJ)

SYSC_MODELS_BUILD=$(SYSC_MODELS) $(VLT_TRACEOBJ)

prepare_vlt: prepare_rtl vlt_model_links $(SIM_VLT_DIR)/Vorpsoc_top

prepare-vlt: prepare-rtl vlt_model_links $(SIM_VLT_DIR)/Vorpsoc_top

        @echo;echo "\tCycle-accurate model compiled successfully"

        @echo;echo "\tCycle-accurate model compiled successfully"

        @echo;echo "\tRun the executable with the -h option for usage instructions:";echo

        @echo;echo "\tRun the executable with the -h option for usage instructions:";echo

        $(SIM_VLT_DIR)/Vorpsoc_top -h

        $(SIM_VLT_DIR)/Vorpsoc_top -h

        @echo;echo

        @echo;echo

Line 642...

Line 650...

# Now compile the top level systemC "testbench" module from the systemC source path

# Now compile the top level systemC "testbench" module from the systemC source path

$(SIM_VLT_DIR)/OrpsocMain.o: $(BENCH_SYSC_SRC_DIR)/OrpsocMain.cpp

$(SIM_VLT_DIR)/OrpsocMain.o: $(BENCH_SYSC_SRC_DIR)/OrpsocMain.cpp

        @echo; echo "\tCompiling top level SystemC testbench"; echo

        @echo; echo "\tCompiling top level SystemC testbench"; echo

        cd $(SIM_VLT_DIR) && g++ $(VLT_DEBUG_COMPILE_FLAGS) $(VLT_CPPFLAGS) $(TRACE_FLAGS) -I$(BENCH_SYSC_INCLUDE_DIR) -I$(SIM_VLT_DIR) -I$(VERILATOR_ROOT)/include -I$(SYSTEMC)/include -c $(BENCH_SYSC_SRC_DIR)/OrpsocMain.cpp

        cd $(SIM_VLT_DIR) && g++ $(VLT_DEBUG_COMPILE_FLAGS) $(VLT_CPPFLAGS) $(TRACE_FLAGS) -I$(BENCH_SYSC_INCLUDE_DIR) -I$(SIM_VLT_DIR) -I$(VERILATOR_ROOT)/include -I$(SYSTEMC)/include -c $(BENCH_SYSC_SRC_DIR)/OrpsocMain.cpp

$(SIM_VLT_DIR)/libVorpsoc_top.a: $(SIM_VLT_DIR)/Vorpsoc_top__ALL.a vlt_modules_compile $(SIM_VLT_DIR)/verilated.o

$(SIM_VLT_DIR)/libVorpsoc_top.a: $(SIM_VLT_DIR)/Vorpsoc_top__ALL.a vlt-modules-compile $(SIM_VLT_DIR)/verilated.o

# Now archive all of the libraries from verilator witht he other modules we might have

# Now archive all of the libraries from verilator witht he other modules we might have

        @echo; echo "\tArchiving libraries into libVorpsoc_top.a"; echo

        @echo; echo "\tArchiving libraries into libVorpsoc_top.a"; echo

        @cd $(SIM_VLT_DIR) && \

        $(Q)cd $(SIM_VLT_DIR) && \

        cp Vorpsoc_top__ALL.a libVorpsoc_top.a && \

        cp Vorpsoc_top__ALL.a libVorpsoc_top.a && \

        ar rcs libVorpsoc_top.a verilated.o; \

        ar rcs libVorpsoc_top.a verilated.o; \

        for SYSCMODEL in $(SYSC_MODELS_BUILD); do \

        for SYSCMODEL in $(SYSC_MODELS_BUILD); do \

                ar rcs libVorpsoc_top.a $$SYSCMODEL.o; \

                ar rcs libVorpsoc_top.a $$SYSCMODEL.o; \

        done

        done

$(SIM_VLT_DIR)/verilated.o:

$(SIM_VLT_DIR)/verilated.o:

        @echo; echo "\tCompiling verilated.o"; echo

        @echo; echo "\tCompiling verilated.o"; echo

        @cd $(SIM_VLT_DIR) && \

        $(Q)cd $(SIM_VLT_DIR) && \

        export CXXFLAGS=$(VLT_DEBUG_COMPILE_FLAGS); \

        export CXXFLAGS=$(VLT_DEBUG_COMPILE_FLAGS); \

        export USER_CPPFLAGS="$(VLT_CPPFLAGS)"; \

        export USER_CPPFLAGS="$(VLT_CPPFLAGS)"; \

        export USER_LDDFLAGS="$(VLT_CPPFLAGS)"; \

        export USER_LDDFLAGS="$(VLT_CPPFLAGS)"; \

        $(MAKE) -f Vorpsoc_top.mk verilated.o

        $(MAKE) -f Vorpsoc_top.mk verilated.o

.PHONY: vlt_modules_compile

.PHONY: vlt-modules-compile

vlt_modules_compile:

vlt-modules-compile:

# Compile the module files

# Compile the module files

        @echo; echo "\tCompiling SystemC models"

        @echo; echo "\tCompiling SystemC models"

        @cd $(SIM_VLT_DIR) && \

        $(Q)cd $(SIM_VLT_DIR) && \

        for SYSCMODEL in $(SYSC_MODELS_BUILD); do \

        for SYSCMODEL in $(SYSC_MODELS_BUILD); do \

                echo;echo "\t$$SYSCMODEL"; echo; \

                echo;echo "\t$$SYSCMODEL"; echo; \

                export CXXFLAGS=$(VLT_DEBUG_COMPILE_FLAGS); \

                export CXXFLAGS=$(VLT_DEBUG_COMPILE_FLAGS); \

                export USER_CPPFLAGS="$(VLT_CPPFLAGS) -I$(BENCH_SYSC_INCLUDE_DIR)"; \

                export USER_CPPFLAGS="$(VLT_CPPFLAGS) -I$(BENCH_SYSC_INCLUDE_DIR)"; \

                export USER_LDDFLAGS="$(VLT_CPPFLAGS)"; \

                export USER_LDDFLAGS="$(VLT_CPPFLAGS)"; \

                 $(MAKE) -f Vorpsoc_top.mk $$SYSCMODEL.o; \

                 $(MAKE) -f Vorpsoc_top.mk $$SYSCMODEL.o; \

        done

        done

$(SIM_VLT_DIR)/Vorpsoc_top__ALL.a: $(SIM_VLT_DIR)/Vorpsoc_top.mk

$(SIM_VLT_DIR)/Vorpsoc_top__ALL.a: $(SIM_VLT_DIR)/Vorpsoc_top.mk

        @echo; echo "\tCompiling main design"; echo

        @echo; echo "\tCompiling main design"; echo

        @cd $(SIM_VLT_DIR) && \

        $(Q)cd $(SIM_VLT_DIR) && \

        export USER_CPPFLAGS="$(VLT_CPPFLAGS)"; \

        export USER_CPPFLAGS="$(VLT_CPPFLAGS)"; \

        export USER_LDDFLAGS="$(VLT_CPPFLAGS)"; \

        export USER_LDDFLAGS="$(VLT_CPPFLAGS)"; \

        $(MAKE) -f Vorpsoc_top.mk Vorpsoc_top__ALL.a

        $(MAKE) -f Vorpsoc_top.mk Vorpsoc_top__ALL.a

$(SIM_VLT_DIR)/Vorpsoc_top.mk: $(SIM_VLT_DIR)/$(VLT_COMMAND_FILE).generated $(SIM_VLT_DIR)/libmodules.a

$(SIM_VLT_DIR)/Vorpsoc_top.mk: $(SIM_VLT_DIR)/$(VLT_COMMAND_FILE).generated $(SIM_VLT_DIR)/libmodules.a

Line 689...

Line 697...

        verilator -language 1364-2001 -Wno-lint --top-module orpsoc_top $(VLT_DEBUG_OPTIONS) -Mdir . -sc $(VLT_FLAGS) -I$(BENCH_SYSC_INCLUDE_DIR) -I$(BENCH_SYSC_SRC_DIR) -f $(VLT_COMMAND_FILE).generated

        verilator -language 1364-2001 -Wno-lint --top-module orpsoc_top $(VLT_DEBUG_OPTIONS) -Mdir . -sc $(VLT_FLAGS) -I$(BENCH_SYSC_INCLUDE_DIR) -I$(BENCH_SYSC_SRC_DIR) -f $(VLT_COMMAND_FILE).generated

# SystemC modules library

# SystemC modules library

$(SIM_VLT_DIR)/libmodules.a:

$(SIM_VLT_DIR)/libmodules.a:

        @echo; echo "\tCompiling SystemC modules"; echo

        @echo; echo "\tCompiling SystemC modules"; echo

        @export VLT_CPPFLAGS="$(VLT_CPPFLAGS)"; \

        $(Q)export VLT_CPPFLAGS="$(VLT_CPPFLAGS)"; \

        $(MAKE) -C $(BENCH_SYSC_SRC_DIR) -f $(BENCH_SYSC_SRC_DIR)/Modules.make $(VLT_SYSC_DEBUG_DEFINE)

        $(MAKE) -C $(BENCH_SYSC_SRC_DIR) -f $(BENCH_SYSC_SRC_DIR)/Modules.make $(VLT_SYSC_DEBUG_DEFINE)

ALL_VLOG=$(shell find $(RTL_VERILOG_DIR) -name "*.v")

ALL_VLOG=$(shell find $(RTL_VERILOG_DIR) -name "*.v")

# Verilator command script

# Verilator command script

# Generate the compile script to give Verilator - make it sensitive to the RTL

# Generate the compile script to give Verilator - make it sensitive to the RTL

$(SIM_VLT_DIR)/$(VLT_COMMAND_FILE).generated: $(ALL_VLOG)

$(SIM_VLT_DIR)/$(VLT_COMMAND_FILE).generated: $(ALL_VLOG)

        @echo; echo "\tGenerating verilator compile script"; echo

        @echo; echo "\tGenerating verilator compile script"; echo

        @sed < $(SIM_BIN_DIR)/$(VLT_COMMAND_FILE) > $(SIM_VLT_DIR)/$(VLT_COMMAND_FILE).generated \

        $(Q)sed < $(SIM_BIN_DIR)/$(VLT_COMMAND_FILE) > $(SIM_VLT_DIR)/$(VLT_COMMAND_FILE).generated \

                -e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)!              \

                -e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)!              \

                -e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)!                  \

                -e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)!                  \

                -e s!\$$BACKEND_DIR!$(BACKEND_DIR)!                  \

                -e s!\$$BACKEND_DIR!$(BACKEND_DIR)!                  \

                -e \\!^//.*\$$!d -e \\!^\$$!d;

                -e \\!^//.*\$$!d -e \\!^\$$!d;

.PHONY: vlt_model_links

.PHONY: vlt_model_links

vlt_model_links:

vlt_model_links:

# Link all the required system C model files into the verilator work dir

# Link all the required system C model files into the verilator work dir

        @echo; echo "\tLinking SystemC model source to verilator build path"; echo

        @echo; echo "\tLinking SystemC model source to verilator build path"; echo

        @if [ ! -d $(SIM_VLT_DIR) ]; then mkdir $(SIM_VLT_DIR); fi

        @if [ ! -d $(SIM_VLT_DIR) ]; then mkdir $(SIM_VLT_DIR); fi

        @cd $(SIM_VLT_DIR) && \

        $(Q)cd $(SIM_VLT_DIR) && \

        for SYSCMODEL in $(SYSC_MODELS); do \

        for SYSCMODEL in $(SYSC_MODELS); do \

                if [ ! -e $$SYSCMODEL.cpp ]; then \

                if [ ! -e $$SYSCMODEL.cpp ]; then \

                        ln -s $(BENCH_SYSC_SRC_DIR)/$$SYSCMODEL.cpp .; \

                        ln -s $(BENCH_SYSC_SRC_DIR)/$$SYSCMODEL.cpp .; \

                        ln -s $(BENCH_SYSC_INCLUDE_DIR)/$$SYSCMODEL.h .; \

                        ln -s $(BENCH_SYSC_INCLUDE_DIR)/$$SYSCMODEL.h .; \

                fi; \

                fi; \

Line 724...

Line 732...

################################################################################

################################################################################

# Verilator test loop

# Verilator test loop

################################################################################

################################################################################

# Verilator defaults to internal memories

# Verilator defaults to internal memories

vlt-tests: prepare_sw_uart_printf prepare_rtl prepare_dirs prepare_vlt

vlt-tests: prepare-sw-uart-printf prepare-rtl prepare-dirs prepare-vlt

        @echo

        @echo

        @echo "Beginning loop that will complete the following tests: $(TESTS)"

        @echo "Beginning loop that will complete the following tests: $(TESTS)"

        @echo

        @echo

        @for TEST in $(TESTS); do \

        $(Q)for TEST in $(TESTS); do \

                echo "################################################################################"; \

                echo "################################################################################"; \

                echo; \

                echo; \

                echo "\t#### Current test: $$TEST ####"; echo; \

                echo "\t#### Current test: $$TEST ####"; echo; \

                echo "\t#### Compiling software ####"; echo; \

                echo "\t#### Compiling software ####"; echo; \

                CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \

                CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \

Line 754...

Line 762...

        echo "Test results: "$$TESTS_PASSED" out of "$$TESTS_PERFORMED" tests passed"; echo

        echo "Test results: "$$TESTS_PASSED" out of "$$TESTS_PERFORMED" tests passed"; echo

###############################################################################

###############################################################################

# Verilator profiled module make

# Verilator profiled module make

###############################################################################

###############################################################################

# To run this, first run a "make prepare_vlt VLT_DO_PROFILING=1" then do a

# To run this, first run a "make prepare-vlt VLT_DO_PROFILING=1" then do a

# "make clean" and then a "make prepare_vlt_profiled"

# "make clean" and then a "make prepare-vlt_profiled"

# This new make target copies athe results of the profiling back to the right

# This new make target copies athe results of the profiling back to the right

# paths before we create everything again

# paths before we create everything again

###############################################################################

###############################################################################

prepare_vlt_profiled: vlt_restore_profileoutput prepare_rtl vlt_model_links $(SIM_VLT_DIR)/Vorpsoc_top

prepare-vlt-profiled: vlt_restore-profileoutput prepare-rtl vlt-model-links $(SIM_VLT_DIR)/Vorpsoc_top

vlt_restore_profileoutput:

vlt-restore-profileoutput:

        @echo;echo "\tRestoring profiling outputs"; echo

        @echo;echo "\tRestoring profiling outputs"; echo

        @mkdir -p ../vlt

        $(Q)mkdir -p ../vlt

        @cp /tmp/*.gc* $(SIM_VLT_DIR)

        $(Q)cp /tmp/*.gc* $(SIM_VLT_DIR)

        @cp /tmp/*.gc* $(BENCH_SYSC_SRC_DIR)

        $(Q)cp /tmp/*.gc* $(BENCH_SYSC_SRC_DIR)

################################################################################

################################################################################

# Architectural simulator test loop

# Architectural simulator test loop

################################################################################

################################################################################

# Verilator defaults to internal memories

# Verilator defaults to internal memories

sim-tests: prepare_sw_uart_printf

sim-tests: prepare-sw-uart-printf

        @if [ ! -d $(SIM_RESULTS_DIR) ]; then mkdir -p $(SIM_RESULTS_DIR); fi

        @if [ ! -d $(SIM_RESULTS_DIR) ]; then mkdir -p $(SIM_RESULTS_DIR); fi

        @echo

        @echo

        @echo "Beginning loop that will complete the following tests: $(TESTS)"

        @echo "Beginning loop that will complete the following tests: $(TESTS)"

        @echo

        @echo

        @for TEST in $(TESTS); do \

        $(Q)for TEST in $(TESTS); do \

                echo "################################################################################"; \

                echo "################################################################################"; \

                echo; \

                echo; \

                echo "\t#### Current test: $$TEST ####"; echo; \

                echo "\t#### Current test: $$TEST ####"; echo; \

                echo "\t#### Compiling software ####"; echo; \

                echo "\t#### Compiling software ####"; echo; \

                CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \

                CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \

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