| Line 258... |
Line 258... |
RTL_VERILOG_DIR=$(PROJECT_ROOT)/rtl/verilog
|
RTL_VERILOG_DIR=$(PROJECT_ROOT)/rtl/verilog
|
SW_DIR=$(PROJECT_ROOT)/sw
|
SW_DIR=$(PROJECT_ROOT)/sw
|
|
|
ICARUS=iverilog
|
ICARUS=iverilog
|
ICARUS_VVP=vvp
|
ICARUS_VVP=vvp
|
|
VSIM_COMP=vlog
|
|
VSIM=vsim
|
|
NCVERILOG=ncverilog
|
ICARUS_COMMAND_FILE=icarus.scr
|
ICARUS_COMMAND_FILE=icarus.scr
|
VLT_COMMAND_FILE=verilator.scr
|
VLT_COMMAND_FILE=verilator.scr
|
SIM_SUCCESS_MESSAGE=deaddead
|
SIM_SUCCESS_MESSAGE=deaddead
|
MGC_COMMAND_FILE=modelsim.scr
|
MGC_COMMAND_FILE=modelsim.scr
|
|
|
| Line 281... |
Line 284... |
# to do it this way than make them all include a file.
|
# to do it this way than make them all include a file.
|
ifdef USE_SDRAM
|
ifdef USE_SDRAM
|
EVENT_SIM_FLAGS += "-D USE_SDRAM=$(USE_SDRAM)"
|
EVENT_SIM_FLAGS += "-D USE_SDRAM=$(USE_SDRAM)"
|
endif
|
endif
|
|
|
# Set SIMULATOR=vsim on command line to use Modelsim
|
# Enable ethernet if defined on the command line
|
ifeq ($(SIMULATOR), vsim)
|
ifdef USE_ETHERNET
|
# Modelsim
|
EVENT_SIM_FLAGS += "-D USE_ETHERNET=$(USE_ETHERNET) -D USE_ETHERNET_IO=$(USE_ETHERNET)"
|
SIM_COMMANDFILE=$(MGC_COMMAND_FILE)
|
# Extra tests we do if ethernet is enabled
|
else
|
TESTS += eth-basic eth-int
|
|
endif
|
|
|
|
#Default simulator is Icarus Verilog
|
|
# Set SIMULATOR=vsim to use Modelsim
|
|
# Set SIMULATOR=ncverilog to use Cadence's NC-Verilog
|
|
SIMULATOR ?= $(ICARUS)
|
|
|
|
# Set the command file to use, simulator dependent
|
|
ifeq ($(SIMULATOR), $(ICARUS))
|
# Icarus Verilog Simulator
|
# Icarus Verilog Simulator
|
SIM_COMMANDFILE=$(ICARUS_COMMAND_FILE)
|
SIM_COMMANDFILE=$(ICARUS_COMMAND_FILE)
|
endif
|
endif
|
|
|
|
ifeq ($(SIMULATOR), $(VSIM))
|
|
# Modelsim has own command file (it's a little more stupid than Icarus & NC)
|
|
SIM_COMMANDFILE=$(MGC_COMMAND_FILE)
|
|
endif
|
|
|
|
ifeq ($(SIMULATOR), $(NCVERILOG))
|
|
# NCVerilog uses same command file as Icarus
|
|
SIM_COMMANDFILE=$(ICARUS_COMMAND_FILE)
|
|
endif
|
|
|
GENERATED_COMMANDFILE=$(SIM_COMMANDFILE).generated
|
GENERATED_COMMANDFILE=$(SIM_COMMANDFILE).generated
|
|
|
# When Modelsim is selected as simulator, we compile
|
# When Modelsim is selected as simulator, we compile
|
# the ORPSoC system into one library called orpsoc and
|
# the ORPSoC system into one library called orpsoc and
|
# then simply re-compile the testbench and or1200_monitor
|
# then simply re-compile the testbench and or1200_monitor
|
| Line 307... |
Line 329... |
ifeq ($(VCD), 1)
|
ifeq ($(VCD), 1)
|
VOPT_ARGS=-voptargs="+acc=rnp"
|
VOPT_ARGS=-voptargs="+acc=rnp"
|
endif
|
endif
|
|
|
# Simulation compile and run commands, depending on your
|
# Simulation compile and run commands, depending on your
|
# simulator. Currently only Modelsim (vsim) and Icarus right
|
# simulator.
|
# now.
|
|
# TODO: Put the NC-sim commands in here too and have just the
|
# Icarus Verilog
|
# single simulation test loop rule.
|
ifeq ($(SIMULATOR), $(ICARUS))
|
ifeq ($(SIMULATOR), vsim)
|
# Icarus Verilog Simulator compile and run commands
|
|
SIM_COMMANDCOMPILE=rm -f $(SIM_RUN_DIR)/a.out; $(ICARUS) -sorpsoc_testbench -c $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE) $(EVENT_SIM_FLAGS)
|
|
# Icarus Verilog run command
|
|
SIM_COMMANDRUN=$(ICARUS_VVP) -l $(SIM_RESULTS_DIR)/$$TEST-vvp-out.log a.out
|
|
endif
|
|
|
|
# Modelsim
|
|
ifeq ($(SIMULATOR), $(VSIM))
|
# Line to compile the orpsoc design into a modelsim library.
|
# Line to compile the orpsoc design into a modelsim library.
|
SIM_COMMANDCOMPILE=if [ ! -e work ]; then vlib work; vlib $(MGC_ORPSOC_LIB); vlog -work orpsoc -f $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE); fi
|
SIM_COMMANDCOMPILE=if [ ! -e work ]; then vlib work; vlib $(MGC_ORPSOC_LIB); vlog -work orpsoc -f $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE); fi
|
# Final modelsim compile, done each time, pulling in or1200
|
# Final modelsim compile, done each time, pulling in or1200
|
# monitor and the new test_defines.v file:
|
# monitor and the new test_defines.v file:
|
VSIM_COMPILE_TB=vlog +incdir+. +incdir+$(BENCH_VERILOG_DIR) +incdir+$(RTL_VERILOG_DIR) +define+TEST_DEFINE_FILE $(BENCH_VERILOG_DIR)/or1200_monitor.v $(BENCH_VERILOG_DIR)/orpsoc_testbench.v
|
VSIM_COMPILE_TB=vlog +incdir+. +incdir+$(BENCH_VERILOG_DIR) +incdir+$(RTL_VERILOG_DIR) +define+TEST_DEFINE_FILE $(BENCH_VERILOG_DIR)/or1200_monitor.v $(BENCH_VERILOG_DIR)/orpsoc_testbench.v
|
# Simulation run command:
|
# Simulation run command:
|
SIM_COMMANDRUN=$(VSIM_COMPILE_TB); vsim -c -quiet +nowarnTFMPC -L $(MGC_ORPSOC_LIB) $(VOPT_ARGS) -do "run -all; exit" orpsoc_testbench
|
SIM_COMMANDRUN=$(VSIM_COMPILE_TB); $(VSIM) -c -quiet +nowarnTFMPC -L $(MGC_ORPSOC_LIB) $(VOPT_ARGS) -do "run -all; exit" orpsoc_testbench
|
else
|
|
# Icarus Verilog Simulator compile command
|
|
SIM_COMMANDCOMPILE=rm -f $(SIM_RUN_DIR)/a.out; $(ICARUS) -sorpsoc_testbench -c $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE) $(EVENT_SIM_FLAGS)
|
|
# Icarus Verilog run command
|
|
SIM_COMMANDRUN=$(ICARUS_VVP) -l $(SIM_RESULTS_DIR)/$$TEST-vvp-out.log a.out
|
|
endif
|
endif
|
|
|
# Enable ethernet if defined on the command line
|
# NCVerilog
|
ifdef USE_ETHERNET
|
ifeq ($(SIMULATOR), $(NCVERILOG))
|
EVENT_SIM_FLAGS += "-D USE_ETHERNET=$(USE_ETHERNET) -D USE_ETHERNET_IO=$(USE_ETHERNET)"
|
SIM_COMMANDCOMPILE=echo
|
# Extra tests we do if ethernet is enabled
|
SIM_COMMANDRUN=$(NCVERILOG) -f $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE) -Q -l $(SIM_RESULTS_DIR)/$$TEST-$(NCVERILOG)-out.log $(EVENT_SIM_FLAGS)
|
TESTS += eth-basic eth-int
|
|
endif
|
endif
|
|
|
|
# Names of memory files used in simulation
|
SIM_FLASH_MEM_FILE="flash.in"
|
SIM_FLASH_MEM_FILE="flash.in"
|
FLASH_MEM_FILE_SUFFIX="-twobyte-sizefirst.hex"
|
FLASH_MEM_FILE_SUFFIX="-twobyte-sizefirst.hex"
|
SIM_SRAM_MEM_FILE="sram.vmem"
|
SIM_SRAM_MEM_FILE="sram.vmem"
|
|
|
TESTS_PASSED=0
|
TESTS_PASSED=0
|
TESTS_PERFORMED=0;
|
TESTS_PERFORMED=0;
|
|
|
################################################################################
|
################################################################################
|
# Event-driven simulator build rules (Icarus, NCSim)
|
# Event-driven simulator build rules
|
################################################################################
|
################################################################################
|
|
|
$(RTL_VERILOG_DIR)/components/wb_sdram_ctrl/wb_sdram_ctrl_fsm.v:
|
$(RTL_VERILOG_DIR)/components/wb_sdram_ctrl/wb_sdram_ctrl_fsm.v:
|
@cd $(RTL_VERILOG_DIR)/components/wb_sdram_ctrl && perl fizzim.pl -encoding onehot -terse < wb_sdram_ctrl_fsm.fzm > wb_sdram_ctrl_fsm.v
|
@cd $(RTL_VERILOG_DIR)/components/wb_sdram_ctrl && perl fizzim.pl -encoding onehot -terse < wb_sdram_ctrl_fsm.fzm > wb_sdram_ctrl_fsm.v
|
|
|
| Line 359... |
Line 383... |
-e s!\$$BACKEND_DIR!$(BACKEND_DIR)! \
|
-e s!\$$BACKEND_DIR!$(BACKEND_DIR)! \
|
-e \\!^//.*\$$!d -e \\!^\$$!d ; \
|
-e \\!^//.*\$$!d -e \\!^\$$!d ; \
|
echo "+define+TEST_DEFINE_FILE=\"test_define.v\"" >> $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE); \
|
echo "+define+TEST_DEFINE_FILE=\"test_define.v\"" >> $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE); \
|
if [ ! -z $$VCD ]; \
|
if [ ! -z $$VCD ]; \
|
then echo "+define+VCD" >> $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE); \
|
then echo "+define+VCD" >> $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE); \
|
|
if [ $(SIMULATOR) = $(NCVERILOG) ]; \
|
|
then echo "+access+r" >> $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE); \
|
|
fi; \
|
fi; \
|
fi; \
|
if [ ! -z $$UART_PRINTF ]; \
|
if [ ! -z $$UART_PRINTF ]; \
|
then echo "+define+UART_PRINTF" >> $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE); \
|
then echo "+define+UART_PRINTF" >> $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE); \
|
|
fi; \
|
|
if [ $(SIMULATOR) = $(NCVERILOG) ]; \
|
|
then echo "+nocopyright" >> $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE); \
|
|
echo "+nowarn+MACRDF" >> $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE); \
|
fi
|
fi
|
|
|
ifdef UART_PRINTF
|
ifdef UART_PRINTF
|
TEST_SW_MAKE_OPTS="UART_PRINTF=1"
|
TEST_SW_MAKE_OPTS="UART_PRINTF=1"
|
endif
|
endif
|
| Line 405... |
Line 436... |
# * Logging enabled
|
# * Logging enabled
|
#
|
#
|
# Options:
|
# Options:
|
# SIMULATOR=vsim
|
# SIMULATOR=vsim
|
# Use Mentor Graphics Modelsim simulator
|
# Use Mentor Graphics Modelsim simulator
|
|
# SIMULATOR=ncverilog
|
|
# Use Cadence's NC-Verilog
|
# USE_SDRAM=1
|
# USE_SDRAM=1
|
# Enable use of SDRAM - changes boot sequence and takes
|
# Enable use of SDRAM - changes boot sequence and takes
|
# a lot longer due to application being loaded out of
|
# a lot longer due to application being loaded out of
|
# external FLASH memory and into SDRAM before execution
|
# external FLASH memory and into SDRAM before execution
|
# from the SDRAM.
|
# from the SDRAM.
|
| Line 465... |
Line 498... |
if [ $$? -gt 0 ]; then exit $$?; fi; \
|
if [ $$? -gt 0 ]; then exit $$?; fi; \
|
TEST_RESULT=`cat $(SIM_RESULTS_DIR)/$$TEST-general.log | grep report | grep $(SIM_SUCCESS_MESSAGE) -c`; \
|
TEST_RESULT=`cat $(SIM_RESULTS_DIR)/$$TEST-general.log | grep report | grep $(SIM_SUCCESS_MESSAGE) -c`; \
|
echo; echo "\t####"; \
|
echo; echo "\t####"; \
|
if [ $$TEST_RESULT -gt 0 ]; then \
|
if [ $$TEST_RESULT -gt 0 ]; then \
|
echo "\t#### Test $$TEST PASSED ####";TESTS_PASSED=`expr $$TESTS_PASSED + 1`;\
|
echo "\t#### Test $$TEST PASSED ####";TESTS_PASSED=`expr $$TESTS_PASSED + 1`;\
|
else echo "\t#### Test $$TEST FAILED ####";\
|
|
fi; \
|
|
echo "\t####"; echo; \
|
|
TESTS_PERFORMED=`expr $$TESTS_PERFORMED + 1`;\
|
|
done; \
|
|
echo "Test results: "$$TESTS_PASSED" out of "$$TESTS_PERFORMED" tests passed"; echo
|
|
|
|
|
|
|
|
# Use NCSIM instead of icarus
|
|
rtl-nc-tests: prepare-sw prepare-rtl prepare-dirs
|
|
@echo
|
|
@echo "Beginning loop that will complete the following tests: $(TESTS)"
|
|
@echo
|
|
$(Q)for TEST in $(TESTS); do \
|
|
echo "################################################################################"; \
|
|
echo; \
|
|
echo "\t#### Current test: $$TEST ####"; echo; \
|
|
echo "\t#### Compiling software ####"; echo; \
|
|
CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
|
|
$(MAKE) -C $$CURRENT_TEST_SW_DIR $$TEST; \
|
|
rm -f $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \
|
|
rm -f $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
|
|
ln -s $$CURRENT_TEST_SW_DIR/$$TEST_twobyte_sizefirst.hex $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \
|
|
ln -s $$CURRENT_TEST_SW_DIR/$$TEST_fourbyte.hex $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
|
|
sed < $(SIM_BIN_DIR)/$(ICARUS_COMMAND_FILE) > $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated \
|
|
-e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)! \
|
|
-e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)! \
|
|
-e s!\$$BACKEND_DIR!$(BACKEND_DIR)! \
|
|
-e \\!^//.*\$$!d -e \\!^\$$!d ; \
|
|
echo "+define+TEST_DEFINE_FILE=\"test_define.v\"" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
|
|
if [ ! -z $$VCD ]; \
|
|
then echo "+define+VCD" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
|
|
echo "+access+r" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
|
|
fi; \
|
|
if [ ! -z $$UART_PRINTF ]; \
|
|
then echo "+define+UART_PRINTF" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
|
|
fi; \
|
|
if [ ! -z $$USE_SDRAM ]; then \
|
|
echo "\`define USE_SDRAM" >> $(SIM_RUN_DIR)/test_define.v; \
|
|
fi; \
|
|
if echo $$TEST | grep -q -i ^eth; then \
|
|
echo "\`define ENABLE_ETH_STIM" >> $(SIM_RUN_DIR)/test_define.v; \
|
|
echo "\`define ETH_PHY_VERBOSE" >> $(SIM_RUN_DIR)/test_define.v; \
|
|
fi; \
|
|
echo "+nocopyright" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
|
|
echo "+nowarn+MACRDF" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
|
|
echo "\`define TEST_NAME_STRING \"$$TEST\"" > $(SIM_RUN_DIR)/test_define.v; \
|
|
echo "\`define TEST_RESULTS_DIR \"$(SIM_RESULTS_DIR)/\" " >> $(SIM_RUN_DIR)/test_define.v; \
|
|
if [ -z $$NO_SIM_LOGGING ]; then \
|
|
echo "\`define OR1200_DISPLAY_ARCH_STATE" >> $(SIM_RUN_DIR)/test_define.v; \
|
|
fi; \
|
|
echo ; \
|
|
echo "\t#### Beginning simulation ####"; \
|
|
time -p ncverilog -f $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated -Q -l $(SIM_RESULTS_DIR)/$$TEST-ius-out.log $(EVENT_SIM_FLAGS); \
|
|
if [ $$? -gt 0 ]; then exit $$?; fi; \
|
|
TEST_RESULT=`cat $(SIM_RESULTS_DIR)/$$TEST-general.log | grep report | grep $(SIM_SUCCESS_MESSAGE) -c`; \
|
|
echo; echo "\t####"; \
|
|
if [ $$TEST_RESULT -gt 0 ]; then \
|
|
echo "\t#### Test $$TEST PASSED ####";TESTS_PASSED=`expr $$TESTS_PASSED + 1`;\
|
|
else echo "\t#### Test $$TEST FAILED ####";\
|
else echo "\t#### Test $$TEST FAILED ####";\
|
fi; \
|
fi; \
|
echo "\t####"; echo; \
|
echo "\t####"; echo; \
|
TESTS_PERFORMED=`expr $$TESTS_PERFORMED + 1`;\
|
TESTS_PERFORMED=`expr $$TESTS_PERFORMED + 1`;\
|
done; \
|
done; \
|
