| Line 262... |
Line 262... |
ICARUS=iverilog
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ICARUS=iverilog
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ICARUS_VVP=vvp
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ICARUS_VVP=vvp
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VSIM_COMP=vlog
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VSIM_COMP=vlog
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VSIM=vsim
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VSIM=vsim
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NCVERILOG=ncverilog
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NCVERILOG=ncverilog
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SILOS=silos
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ICARUS_COMMAND_FILE=icarus.scr
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ICARUS_COMMAND_FILE=icarus.scr
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VLT_COMMAND_FILE=verilator.scr
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VLT_COMMAND_FILE=verilator.scr
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SIM_SUCCESS_MESSAGE=deaddead
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SIM_SUCCESS_MESSAGE=deaddead
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MGC_COMMAND_FILE=modelsim.scr
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MGC_COMMAND_FILE=modelsim.scr
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| Line 316... |
Line 317... |
ifeq ($(SIMULATOR), $(NCVERILOG))
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ifeq ($(SIMULATOR), $(NCVERILOG))
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# NCVerilog uses same command file as Icarus
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# NCVerilog uses same command file as Icarus
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SIM_COMMANDFILE=$(ICARUS_COMMAND_FILE)
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SIM_COMMANDFILE=$(ICARUS_COMMAND_FILE)
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endif
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endif
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|
|
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ifeq ($(SIMULATOR), $(SILOS))
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# SILOS uses same command file as Icarus (this should be default)
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|
SIM_COMMANDFILE=$(ICARUS_COMMAND_FILE)
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endif
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|
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|
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GENERATED_COMMANDFILE=$(SIM_COMMANDFILE).generated
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GENERATED_COMMANDFILE=$(SIM_COMMANDFILE).generated
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|
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# When Modelsim is selected as simulator, we compile
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# When Modelsim is selected as simulator, we compile
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# the ORPSoC system into one library called orpsoc and
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# the ORPSoC system into one library called orpsoc and
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# then simply re-compile the testbench and or1200_monitor
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# then simply re-compile the testbench and or1200_monitor
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| Line 363... |
Line 370... |
ifeq ($(SIMULATOR), $(NCVERILOG))
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ifeq ($(SIMULATOR), $(NCVERILOG))
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SIM_COMMANDCOMPILE=echo
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SIM_COMMANDCOMPILE=echo
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SIM_COMMANDRUN=$(NCVERILOG) -f $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE) -Q -l $(SIM_RESULTS_DIR)/$$TEST-$(NCVERILOG)-out.log $(EVENT_SIM_FLAGS)
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SIM_COMMANDRUN=$(NCVERILOG) -f $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE) -Q -l $(SIM_RESULTS_DIR)/$$TEST-$(NCVERILOG)-out.log $(EVENT_SIM_FLAGS)
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endif
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endif
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|
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# Silos
|
|
ifeq ($(SIMULATOR), $(SILOS))
|
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SIM_COMMANDCOMPILE=echo
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SIM_COMMANDRUN=$(SILOS) -b -w -f $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE) -l $(SIM_RESULTS_DIR)/$$TEST-$(SILOS)-out.log $(EVENT_SIM_FLAGS)
|
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endif
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|
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# Names of memory files used in simulation
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# Names of memory files used in simulation
|
SIM_FLASH_MEM_FILE="flash.in"
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SIM_FLASH_MEM_FILE="flash.in"
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FLASH_MEM_FILE_SUFFIX="-twobyte-sizefirst.hex"
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FLASH_MEM_FILE_SUFFIX="-twobyte-sizefirst.hex"
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SIM_SRAM_MEM_FILE="sram.vmem"
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SIM_SRAM_MEM_FILE="sram.vmem"
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| Line 500... |
Line 514... |
echo "\t#### Compiling RTL ####"; \
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echo "\t#### Compiling RTL ####"; \
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$(SIM_COMMANDCOMPILE); \
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$(SIM_COMMANDCOMPILE); \
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echo; \
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echo; \
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echo "\t#### Beginning simulation ####"; \
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echo "\t#### Beginning simulation ####"; \
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time -p $(SIM_COMMANDRUN) ; \
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time -p $(SIM_COMMANDRUN) ; \
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if [ $$? -gt 0 ]; then exit $$?; fi; \
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if [ $$? -gt 0 && $$SIMULATOR -ne $$SILOS]; then exit $$?; fi; \
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TEST_RESULT=`cat $(SIM_RESULTS_DIR)/$$TEST-general.log | grep report | grep $(SIM_SUCCESS_MESSAGE) -c`; \
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TEST_RESULT=`cat $(SIM_RESULTS_DIR)/$$TEST-general.log | grep report | grep $(SIM_SUCCESS_MESSAGE) -c`; \
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echo; echo "\t####"; \
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echo; echo "\t####"; \
|
if [ $$TEST_RESULT -gt 0 ]; then \
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if [ $$TEST_RESULT -gt 0 ]; then \
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echo "\t#### Test $$TEST PASSED ####";TESTS_PASSED=`expr $$TESTS_PASSED + 1`;\
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echo "\t#### Test $$TEST PASSED ####";TESTS_PASSED=`expr $$TESTS_PASSED + 1`;\
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else echo "\t#### Test $$TEST FAILED ####";\
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else echo "\t#### Test $$TEST FAILED ####";\
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