| Line 11... |
Line 11... |
#### * Test if each software test file gets made properly ####
|
#### * Test if each software test file gets made properly ####
|
#### before it's run in whatever model we're using ####
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#### before it's run in whatever model we're using ####
|
#### * Expand software test-suite (uClibc, ecos tests, LTP?) ####
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#### * Expand software test-suite (uClibc, ecos tests, LTP?) ####
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#### ####
|
#### ####
|
#### Author(s): ####
|
#### Author(s): ####
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#### - jb, jb@orsoc.se ####
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#### - Julius Baxter, julius.baxter@orsoc.se ####
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#### ####
|
#### ####
|
#### ####
|
#### ####
|
######################################################################
|
######################################################################
|
#### ####
|
#### ####
|
#### Copyright (C) 2009 Authors and OPENCORES.ORG ####
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#### Copyright (C) 2009,2010 Authors and OPENCORES.ORG ####
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#### ####
|
#### ####
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#### This source file may be used and distributed without ####
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#### This source file may be used and distributed without ####
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#### restriction provided that this copyright statement is not ####
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#### restriction provided that this copyright statement is not ####
|
#### removed from the file and that any derivative work contains ####
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#### removed from the file and that any derivative work contains ####
|
#### the original copyright notice and the associated disclaimer. ####
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#### the original copyright notice and the associated disclaimer. ####
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| Line 239... |
Line 239... |
# The root path of the whole project
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# The root path of the whole project
|
PROJECT_ROOT ?=$(CUR_DIR)/../..
|
PROJECT_ROOT ?=$(CUR_DIR)/../..
|
|
|
# Tests is only defined if it wasn't already defined when make was called
|
# Tests is only defined if it wasn't already defined when make was called
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# This is the default list of every test that is currently possible
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# This is the default list of every test that is currently possible
|
TESTS ?= basic-nocache cbasic-nocache-O2 dhry-nocache-O2 except-nocache mmu-nocache mul-nocache-O2 syscall-nocache tick-nocache uart-nocache basic-icdc cbasic-icdc-O2 dhry-icdc-O2 except-icdc mmu-icdc mul-icdc-O2 syscall-icdc tick-icdc uart-icdc
|
TESTS ?= or1200-simple or1200-cbasic or1200-dctest or1200-float or1200asm-basic or1200asm-except or1200asm-linkregtest or1200asm-tick or1200asm-ticksyscall uart-simple
|
|
#basic-nocache cbasic-nocache-O2 dhry-nocache-O2 except-nocache mmu-nocache mul-nocache-O2 syscall-nocache tick-nocache uart-nocache basic-icdc cbasic-icdc-O2 dhry-icdc-O2 except-icdc mmu-icdc mul-icdc-O2 syscall-icdc tick-icdc uart-icdc
|
|
|
# Paths to other important parts of this test suite
|
# Paths to other important parts of this test suite
|
SIM_DIR ?=$(PROJECT_ROOT)/sim
|
SIM_DIR ?=$(PROJECT_ROOT)/sim
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SIM_RUN_DIR=$(SIM_DIR)/run
|
SIM_RUN_DIR=$(SIM_DIR)/run
|
SIM_BIN_DIR=$(SIM_DIR)/bin
|
SIM_BIN_DIR=$(SIM_DIR)/bin
|
| Line 265... |
Line 266... |
VSIM=vsim
|
VSIM=vsim
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NCVERILOG=ncverilog
|
NCVERILOG=ncverilog
|
SILOS=silos
|
SILOS=silos
|
ICARUS_COMMAND_FILE=icarus.scr
|
ICARUS_COMMAND_FILE=icarus.scr
|
VLT_COMMAND_FILE=verilator.scr
|
VLT_COMMAND_FILE=verilator.scr
|
SIM_SUCCESS_MESSAGE=deaddead
|
SIM_SUCCESS_MESSAGE=8000000d
|
MGC_COMMAND_FILE=modelsim.scr
|
MGC_COMMAND_FILE=modelsim.scr
|
|
|
ARCH_SIM_EXE=or32-elf-sim
|
ARCH_SIM_EXE=or32-elf-sim
|
ARCH_SIM_CFG_FILE=or1ksim-orpsocv2.cfg
|
ARCH_SIM_CFG_FILE=or1ksim-orpsocv2.cfg
|
|
|
| Line 348... |
Line 349... |
# simulator.
|
# simulator.
|
|
|
# Icarus Verilog
|
# Icarus Verilog
|
ifeq ($(SIMULATOR), $(ICARUS))
|
ifeq ($(SIMULATOR), $(ICARUS))
|
# Icarus Verilog Simulator compile and run commands
|
# Icarus Verilog Simulator compile and run commands
|
SIM_COMMANDCOMPILE=rm -f $(SIM_RUN_DIR)/a.out; $(ICARUS) -s$(RTL_TESTBENCH_TOP) -c $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE) $(DASH_D_EVENT_SIM_FLAGS)
|
SIM_COMMANDCOMPILE=rm -f $(SIM_RUN_DIR)/rtlsim.elf; $(ICARUS) -s$(RTL_TESTBENCH_TOP) -c $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE) -o rtlsim.elf $(DASH_D_EVENT_SIM_FLAGS)
|
# Icarus Verilog run command
|
# Icarus Verilog run command
|
SIM_COMMANDRUN=$(ICARUS_VVP) -l $(SIM_RESULTS_DIR)/$$TEST-vvp-out.log a.out
|
SIM_COMMANDRUN=$(ICARUS_VVP) -l $(SIM_RESULTS_DIR)/$$TEST-vvp-out.log rtlsim.elf
|
endif
|
endif
|
|
|
# Modelsim
|
# Modelsim
|
ifeq ($(SIMULATOR), $(VSIM))
|
ifeq ($(SIMULATOR), $(VSIM))
|
# Line to compile the orpsoc design into a modelsim library.
|
# Line to compile the orpsoc design into a modelsim library.
|
| Line 488... |
Line 489... |
echo "################################################################################"; \
|
echo "################################################################################"; \
|
echo; \
|
echo; \
|
echo "\t#### Current test: $$TEST ####"; echo; \
|
echo "\t#### Current test: $$TEST ####"; echo; \
|
echo "\t#### Compiling software ####"; echo; \
|
echo "\t#### Compiling software ####"; echo; \
|
CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
|
CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
|
$(MAKE) -C $$CURRENT_TEST_SW_DIR $$TEST $(TEST_SW_MAKE_OPTS); \
|
$(MAKE) -C $$CURRENT_TEST_SW_DIR $$TEST.vmem $(TEST_SW_MAKE_OPTS); \
|
rm -f $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \
|
rm -f $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \
|
rm -f $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
|
rm -f $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
|
ln -s $$CURRENT_TEST_SW_DIR/$$TEST$(FLASH_MEM_FILE_SUFFIX) $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \
|
ln -s $$CURRENT_TEST_SW_DIR/$$TEST$(FLASH_MEM_FILE_SUFFIX) $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \
|
ln -s $$CURRENT_TEST_SW_DIR/$$TEST.vmem $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
|
ln -s $$CURRENT_TEST_SW_DIR/$$TEST.vmem $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
|
echo "\`define TEST_NAME_STRING \"$$TEST\"" > $(SIM_RUN_DIR)/test_define.v; \
|
echo "\`define TEST_NAME_STRING \"$$TEST\"" > $(SIM_RUN_DIR)/test_define.v; \
|
| Line 515... |
Line 516... |
$(SIM_COMMANDCOMPILE); \
|
$(SIM_COMMANDCOMPILE); \
|
echo; \
|
echo; \
|
echo "\t#### Beginning simulation ####"; \
|
echo "\t#### Beginning simulation ####"; \
|
time -p $(SIM_COMMANDRUN) ; \
|
time -p $(SIM_COMMANDRUN) ; \
|
if [ "$$SIMULATOR" != "$$SILOS" ]; then if [ $$? -gt 0 ]; then exit $$?; fi; fi; \
|
if [ "$$SIMULATOR" != "$$SILOS" ]; then if [ $$? -gt 0 ]; then exit $$?; fi; fi; \
|
TEST_RESULT=`cat $(SIM_RESULTS_DIR)/$$TEST-general.log | grep report | grep $(SIM_SUCCESS_MESSAGE) -c`; \
|
TEST_RESULT=`cat $(SIM_RESULTS_DIR)/$$TEST-general.log | grep $(SIM_SUCCESS_MESSAGE) -c`; \
|
echo; echo "\t####"; \
|
echo; echo "\t####"; \
|
if [ $$TEST_RESULT -gt 0 ]; then \
|
if [ $$TEST_RESULT -gt 0 ]; then \
|
echo "\t#### Test $$TEST PASSED ####";TESTS_PASSED=`expr $$TESTS_PASSED + 1`;\
|
echo "\t#### Test $$TEST PASSED ####";TESTS_PASSED=`expr $$TESTS_PASSED + 1`;\
|
else echo "\t#### Test $$TEST FAILED ####";\
|
else echo "\t#### Test $$TEST FAILED ####";\
|
fi; \
|
fi; \
|
| Line 574... |
Line 575... |
$(Q)echo "\`define TEST_NAME_STRING \"$(VPI_TEST_SW)-vpi\"" > $(SIM_RUN_DIR)/test_define.v
|
$(Q)echo "\`define TEST_NAME_STRING \"$(VPI_TEST_SW)-vpi\"" > $(SIM_RUN_DIR)/test_define.v
|
$(Q)echo "\`define TEST_RESULTS_DIR \"$(SIM_RESULTS_DIR)/\" " >> $(SIM_RUN_DIR)/test_define.v
|
$(Q)echo "\`define TEST_RESULTS_DIR \"$(SIM_RESULTS_DIR)/\" " >> $(SIM_RUN_DIR)/test_define.v
|
$(Q)if [ -z $$NO_SIM_LOGGING ]; then echo "\`define OR1200_DISPLAY_ARCH_STATE" >> $(SIM_RUN_DIR)/test_define.v; fi
|
$(Q)if [ -z $$NO_SIM_LOGGING ]; then echo "\`define OR1200_DISPLAY_ARCH_STATE" >> $(SIM_RUN_DIR)/test_define.v; fi
|
@echo
|
@echo
|
@echo "\t#### Compiling RTL ####"
|
@echo "\t#### Compiling RTL ####"
|
$(Q)rm -f $(SIM_RUN_DIR)/a.out
|
$(Q)rm -f $(SIM_RUN_DIR)/rtlsim.elf
|
$(Q)$(ICARUS) -s$(RTL_TESTBENCH_TOP) -c $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated $(EVENT_SIM_FLAGS)
|
$(Q)$(ICARUS) -s$(RTL_TESTBENCH_TOP) -c $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated -o rtlsim.elf $(EVENT_SIM_FLAGS)
|
@echo
|
@echo
|
@echo "\t#### Beginning simulation with VPI debug module enabled ####"; echo
|
@echo "\t#### Beginning simulation with VPI debug module enabled ####"; echo
|
$(Q)$(ICARUS_VVP) $(ICARUS_VPI_OPTS) -l $(SIM_RESULTS_DIR)/$(VPI_TEST_SW)-vvp-out.log a.out
|
$(Q)$(ICARUS_VVP) $(ICARUS_VPI_OPTS) -l $(SIM_RESULTS_DIR)/$(VPI_TEST_SW)-vvp-out.log rtlsim.elf
|
|
|
################################################################################
|
################################################################################
|
# Verilator model build rules
|
# Verilator model build rules
|
################################################################################
|
################################################################################
|
|
|
| Line 744... |
Line 745... |
echo "################################################################################"; \
|
echo "################################################################################"; \
|
echo; \
|
echo; \
|
echo "\t#### Current test: $$TEST ####"; echo; \
|
echo "\t#### Current test: $$TEST ####"; echo; \
|
echo "\t#### Compiling software ####"; echo; \
|
echo "\t#### Compiling software ####"; echo; \
|
CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
|
CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
|
$(MAKE) -C $$CURRENT_TEST_SW_DIR $$TEST $(TEST_SW_MAKE_OPTS) UART_PRINTF=1; \
|
$(MAKE) -C $$CURRENT_TEST_SW_DIR $$TEST.vmem $(TEST_SW_MAKE_OPTS) UART_PRINTF=1; \
|
rm -f $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
|
rm -f $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
|
ln -s $$CURRENT_TEST_SW_DIR/$$TEST.vmem $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
|
ln -s $$CURRENT_TEST_SW_DIR/$$TEST.vmem $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
|
echo "\t#### Beginning simulation ####"; \
|
echo "\t#### Beginning simulation ####"; \
|
time -p $(SIM_VLT_DIR)/Vorpsoc_top $$TEST; \
|
time -p $(SIM_VLT_DIR)/Vorpsoc_top $$TEST; \
|
if [ $$? -gt 0 ]; then exit $$?; fi; \
|
if [ $$? -gt 0 ]; then exit $$?; fi; \
|
| Line 803... |
Line 804... |
echo "################################################################################"; \
|
echo "################################################################################"; \
|
echo; \
|
echo; \
|
echo "\t#### Current test: $$TEST ####"; echo; \
|
echo "\t#### Current test: $$TEST ####"; echo; \
|
echo "\t#### Compiling software ####"; echo; \
|
echo "\t#### Compiling software ####"; echo; \
|
CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
|
CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
|
$(MAKE) -C $$CURRENT_TEST_SW_DIR $$TEST $(TEST_SW_MAKE_OPTS) UART_PRINTF=1; \
|
$(MAKE) -C $$CURRENT_TEST_SW_DIR $$TEST.vmem $(TEST_SW_MAKE_OPTS) UART_PRINTF=1; \
|
rm -f $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
|
rm -f $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
|
ln -s $$CURRENT_TEST_SW_DIR/$$TEST.or32 $(SIM_RUN_DIR)/.; \
|
ln -s $$CURRENT_TEST_SW_DIR/$$TEST.or32 $(SIM_RUN_DIR)/.; \
|
echo;echo "\t#### Launching architectural simulator ####"; \
|
echo;echo "\t#### Launching architectural simulator ####"; \
|
time -p $(ARCH_SIM_EXE) --nosrv -f $(SIM_BIN_DIR)/$(ARCH_SIM_CFG_FILE) $$TEST.or32 > $(SIM_RESULTS_DIR)/$$TEST-or1ksim.log 2>&1; \
|
time -p $(ARCH_SIM_EXE) --nosrv -f $(SIM_BIN_DIR)/$(ARCH_SIM_CFG_FILE) $$TEST.or32 > $(SIM_RESULTS_DIR)/$$TEST-or1ksim.log 2>&1; \
|
if [ $$? -gt 0 ]; then exit $$?; fi; \
|
if [ $$? -gt 0 ]; then exit $$?; fi; \
|
