URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [sim/] [bin/] [Makefile] - Diff between revs 40 and 42

Rev 40	Rev 42
Line 712...	Line 712...
`clean-sim:`	`clean-sim:`
`rm -rf $(SIM_RESULTS_DIR) $(SIM_RUN_DIR)/. $(SIM_VLT_DIR)`	`rm -rf $(SIM_RESULTS_DIR) $(SIM_RUN_DIR)/. $(SIM_VLT_DIR)`

`clean-sysc:`	`clean-sysc:`
`# Clean away dependency files generated by verilator`	`# Clean away dependency files generated by verilator`
`rm -rf $(BENCH_SYSC_SRC_DIR)/*.d`	`$(MAKE) -C $(BENCH_SYSC_SRC_DIR) -f $(BENCH_SYSC_SRC_DIR)/Modules.make clean`

`clean-rtl:`	`clean-rtl:`
`# Clean away temporary verilog source files`	`# Clean away temporary verilog source files`
`rm -f $(RTL_VERILOG_DIR)/intercon.v`	`rm -f $(RTL_VERILOG_DIR)/intercon.v`
`rm -f $(RTL_VERILOG_DIR)/components/wb_sdram_ctrl/wb_sdram_ctrl_fsm.v`	`rm -f $(RTL_VERILOG_DIR)/components/wb_sdram_ctrl/wb_sdram_ctrl_fsm.v`
`No newline at end of file`	`No newline at end of file`