| Line 199... |
Line 199... |
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#
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#
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# SystemC cycle-accurate model compilation
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# SystemC cycle-accurate model compilation
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#
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#
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# A new addition to ORPSoC v2 is the cycle-accurate model. The primary enabler
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# A new addition to ORPSoC v2 is the cycle-accurate model. The primary enabler
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# behind this is verilator, which processes the RTL sources and generates a c++
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# behind this is verilator, which processes the RTL source and generates a c++
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# description of the system. This c++ description is then compiled with a
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# description of the system. This c++ description is then compiled, with a
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# SystemC wrapper. Finally a top-level SystemC testbench instantiates the
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# SystemC wrapper. Finally a top-level SystemC testbench instantiates the
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# model, as well as any other modules - in this case a reset generation, UART
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# model, and other useful modules - in this case a reset generation, UART
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# decoder, and monitor module are included at the top level. These additional
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# decoder, and monitor module are included at the top level. These additional
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# modules and models are written in SystemC and compiled all together with the
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# modules and models are written in SystemC. Finally, everything is linked with
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# cycle-accurate ORPSoC model to create the simulation executable. Finally this
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# the cycle-accurate ORPSoC model to create the simulation executable. This
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# executable is run and should be a cycle-representation of the system. VCDs
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# executable is the cycle-representation of the system.
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# can be generated if enabled. The compiled mentioned above is all done with
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#
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# the GNU c++ compiler, g++.
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# VCDs can be generated if the model is made with VCD=1 specified on the
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# The compilation process is a little more tricky than a typical even-driven
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# command line. Specify a dump file with the "-vcd" option at runtime, eg:
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# "./Vorpsoc_top -vcd dump.vcd"
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# Note that this slows down the simulation.
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#
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# Logging of the processor's execution can be done by specifying a log file
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# on the command line at runtime, eg: "./Vorpsoc_top -log or1200_exec.log"
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# Note that this slows down the simulation.
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#
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# There are performance metrics printed at the conclusion of simulations. To
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# disable these launch the executable with either the -q or --no-perf-summary
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# options. eg: "./Vorpsoc_top -q"
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#
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# The compilation is all done with the GNU c++ compiler, g++.
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#
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# The compilation process is a little more complicated than the event-driven
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# simulator. It proceeds basically by generating the makefiles for compiling
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# simulator. It proceeds basically by generating the makefiles for compiling
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# the design with verilator, running these makes which produces a library
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# the design with verilator, running these makes which produces a library
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# containing the cycle-accurate ORPSoC design, compiling the additional
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# containing the cycle-accurate ORPSoC design, compiling the additional
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# top-level, and testbench, systemC models into a library, and then linking it
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# top-level, and testbench, systemC models into a library, and then linking it
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# all together into the simulation executable.
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# all together into the simulation executable.
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#
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# The major advantage of the cycle-accurate model is that it is quicker, in
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# The major advantage of the cycle-accurate model is that it is quicker, in
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# terms of simulated cycles/second, when compared with event-driven simulators.
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# terms of simulated cycles/second, when compared with event-driven simulators.
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# It is, of course, less accurate in that it cannot model propegation delays.
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# It is, of course, less accurate in that it cannot model propegation delays.
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# However this is usually not an issue for simulating a design which is known
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# However this is usually not an issue for simulating a design which is known
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# to synthesize and run OK. It is very useful for running complex software,
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# to synthesize and run OK. It is very useful for running complex software,
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# such as the linux kernel and real-time OS applications, which generally
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# such as the linux kernel and real-time OS applications, which generally
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# require long simulation times.
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# result in long simulation times.
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#
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# Currently the cycle-accurate model being used doesn't contain much more than
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# Currently the cycle-accurate model being used doesn't contain much more than
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# the processor and a UART, however it's exepected in future this will be
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# the processor and a UART, however it's exepected in future this will be
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# expanded on and more complex software test suites will be implemented to put
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# expanded on and more complex software test suites will be implemented to put
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# the system through its paces.
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# the system through its paces.
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#
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#
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#
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# Name of the directory we're currently in
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# Name of
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# the directory we're currently in
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CUR_DIR=$(shell pwd)
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CUR_DIR=$(shell pwd)
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# The root path of the whole project
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# The root path of the whole project
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PROJECT_ROOT=$(CUR_DIR)/../..
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PROJECT_ROOT=$(CUR_DIR)/../..
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| Line 273... |
Line 288... |
EVENT_SIM_FLAGS += "-D USE_SDRAM=$(USE_SDRAM)"
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EVENT_SIM_FLAGS += "-D USE_SDRAM=$(USE_SDRAM)"
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endif
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endif
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# Enable ethernet if defined on the command line
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# Enable ethernet if defined on the command line
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ifdef USE_ETHERNET
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ifdef USE_ETHERNET
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EVENT_SIM_FLAGS += "-D USE_ETHERNET=$(USE_ETHERNET)"
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EVENT_SIM_FLAGS += "-D USE_ETHERNET=$(USE_ETHERNET) -D USE_ETHERNET_IO=$(USE_ETHERNET)"
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# Extra tests we do if ethernet is enabled
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TESTS += eth-basic
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endif
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endif
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SIM_FLASH_MEM_FILE="flash.in"
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SIM_FLASH_MEM_FILE="flash.in"
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FLASH_MEM_FILE_SUFFIX="-twobyte-sizefirst.hex"
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FLASH_MEM_FILE_SUFFIX="-twobyte-sizefirst.hex"
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SIM_SRAM_MEM_FILE="sram.vmem"
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SIM_SRAM_MEM_FILE="sram.vmem"
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| Line 294... |
Line 311... |
@cd $(RTL_VERILOG_DIR)/components/wb_sdram_ctrl && perl fizzim.pl -encoding onehot -terse < wb_sdram_ctrl_fsm.fzm > wb_sdram_ctrl_fsm.v
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@cd $(RTL_VERILOG_DIR)/components/wb_sdram_ctrl && perl fizzim.pl -encoding onehot -terse < wb_sdram_ctrl_fsm.fzm > wb_sdram_ctrl_fsm.v
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@cd $(RTL_VERILOG_DIR) && sed '/defparam/!s/\([a-zA-Z0-9_]\)\.//g' intercon.vm > intercon.v
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@cd $(RTL_VERILOG_DIR) && sed '/defparam/!s/\([a-zA-Z0-9_]\)\.//g' intercon.vm > intercon.v
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ifdef UART_PRINTF
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ifdef UART_PRINTF
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TEST_SW_MAKE_OPTS=UART_PRINTF=1
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TEST_SW_MAKE_OPTS="UART_PRINTF=1"
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endif
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endif
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.PHONY: prepare_sw
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.PHONY: prepare_sw
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prepare_sw:
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prepare_sw:
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@$(MAKE) -C $(SW_DIR)/support all $(TEST_SW_MAKE_OPTS)
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@$(MAKE) -C $(SW_DIR)/support all $(TEST_SW_MAKE_OPTS)
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| Line 355... |
Line 372... |
# software and linking of the resulting hex file to the run path, etc.
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# software and linking of the resulting hex file to the run path, etc.
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# Main RAM setup - (RTL simulation with Icarus/NCSim only!):
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# Main RAM setup - (RTL simulation with Icarus/NCSim only!):
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# Define USE_SDRAM to enable the external SDRAM, otherwise the simulation
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# Define USE_SDRAM to enable the external SDRAM, otherwise the simulation
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# defaults to an internal SRAM. Eg. $ make rtl-tests USE_SDRAM=1 VCD=1
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# defaults to an internal SRAM. Eg. $ make rtl-tests USE_SDRAM=1 VCD=1
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# Verilator defaults to internal memories
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# Verilator defaults to internal memories
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rtl-tests: prepare_sw_uart_printf prepare_rtl prepare_dirs
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rtl-tests: prepare_sw prepare_rtl prepare_dirs
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@echo
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@echo
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@echo "Beginning loop that will complete the following tests: $(TESTS)"
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@echo "Beginning loop that will complete the following tests: $(TESTS)"
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@echo
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@echo
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@for TEST in $(TESTS); do \
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@for TEST in $(TESTS); do \
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echo "################################################################################"; \
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echo "################################################################################"; \
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| Line 384... |
Line 401... |
if [ ! -z $$UART_PRINTF ]; \
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if [ ! -z $$UART_PRINTF ]; \
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then echo "+define+UART_PRINTF" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
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then echo "+define+UART_PRINTF" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
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fi; \
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fi; \
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echo "\`define TEST_NAME_STRING \"$$TEST\"" > $(SIM_RUN_DIR)/test_define.v; \
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echo "\`define TEST_NAME_STRING \"$$TEST\"" > $(SIM_RUN_DIR)/test_define.v; \
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echo "\`define TEST_RESULTS_DIR \"$(SIM_RESULTS_DIR)/\" " >> $(SIM_RUN_DIR)/test_define.v; \
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echo "\`define TEST_RESULTS_DIR \"$(SIM_RESULTS_DIR)/\" " >> $(SIM_RUN_DIR)/test_define.v; \
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if echo $$TEST | grep -q -i ^eth; then \
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echo "\`define ENABLE_ETH_STIM" >> $(SIM_RUN_DIR)/test_define.v; \
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echo "\`define ETH_PHY_VERBOSE" >> $(SIM_RUN_DIR)/test_define.v; \
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fi; \
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if [ -z $$NO_SIM_LOGGING ]; then \
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if [ -z $$NO_SIM_LOGGING ]; then \
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echo "\`define OR1200_DISPLAY_ARCH_STATE" >> $(SIM_RUN_DIR)/test_define.v; \
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echo "\`define OR1200_DISPLAY_ARCH_STATE" >> $(SIM_RUN_DIR)/test_define.v; \
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fi; \
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fi; \
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echo ; \
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echo ; \
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echo "\t#### Compiling RTL ####"; \
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echo "\t#### Compiling RTL ####"; \
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| Line 440... |
Line 461... |
then echo "+define+UART_PRINTF" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
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then echo "+define+UART_PRINTF" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
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fi; \
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fi; \
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if [ ! -z $$USE_SDRAM ]; then \
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if [ ! -z $$USE_SDRAM ]; then \
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echo "\`define USE_SDRAM" >> $(SIM_RUN_DIR)/test_define.v; \
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echo "\`define USE_SDRAM" >> $(SIM_RUN_DIR)/test_define.v; \
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fi; \
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fi; \
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if echo $$TEST | grep -q -i ^eth; then \
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echo "\`define ENABLE_ETH_STIM" >> $(SIM_RUN_DIR)/test_define.v; \
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echo "\`define ETH_PHY_VERBOSE" >> $(SIM_RUN_DIR)/test_define.v; \
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fi; \
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echo "+nocopyright" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
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echo "+nocopyright" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
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echo "+nowarn+MACRDF" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
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echo "+nowarn+MACRDF" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
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echo "\`define TEST_NAME_STRING \"$$TEST\"" > $(SIM_RUN_DIR)/test_define.v; \
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echo "\`define TEST_NAME_STRING \"$$TEST\"" > $(SIM_RUN_DIR)/test_define.v; \
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echo "\`define TEST_RESULTS_DIR \"$(SIM_RESULTS_DIR)/\" " >> $(SIM_RUN_DIR)/test_define.v; \
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echo "\`define TEST_RESULTS_DIR \"$(SIM_RESULTS_DIR)/\" " >> $(SIM_RUN_DIR)/test_define.v; \
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if [ -z $$NO_SIM_LOGGING ]; then \
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if [ -z $$NO_SIM_LOGGING ]; then \
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| Line 698... |
Line 723... |
################################################################################
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################################################################################
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clean: clean-sw clean-sim clean-sysc clean-rtl clean_vpi
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clean: clean-sw clean-sim clean-sysc clean-rtl clean_vpi
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clean-sw:
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clean-sw:
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@for TEST in $(TESTS); do \
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@for SWDIR in `ls $(SW_DIR)`; do \
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echo "Current test: $$TEST"; \
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echo $$SWDIR; \
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CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
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$(MAKE) -C $(SW_DIR)/$$SWDIR clean; \
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echo "Current test sw directory: " $$CURRENT_TEST_SW_DIR; \
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$(MAKE) -C $$CURRENT_TEST_SW_DIR clean; \
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done
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done
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$(MAKE) -C $(SW_DIR)/support clean
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$(MAKE) -C $(SW_DIR)/utils clean
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clean-sim:
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clean-sim:
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rm -rf $(SIM_RESULTS_DIR) $(SIM_RUN_DIR)/*.* $(SIM_VLT_DIR)
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rm -rf $(SIM_RESULTS_DIR) $(SIM_RUN_DIR)/*.* $(SIM_VLT_DIR)
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clean-sysc:
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clean-sysc:
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| Line 718... |
Line 739... |
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clean-rtl:
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clean-rtl:
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# Clean away temporary verilog source files
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# Clean away temporary verilog source files
|
rm -f $(RTL_VERILOG_DIR)/intercon.v
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rm -f $(RTL_VERILOG_DIR)/intercon.v
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rm -f $(RTL_VERILOG_DIR)/components/wb_sdram_ctrl/wb_sdram_ctrl_fsm.v
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rm -f $(RTL_VERILOG_DIR)/components/wb_sdram_ctrl/wb_sdram_ctrl_fsm.v
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No newline at end of file
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No newline at end of file
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