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Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [sim/] [bin/] [Makefile] - Diff between revs 476 and 485

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Rev 476 Rev 485
Line 95... Line 95...
SIM_DIR ?=$(PROJECT_ROOT)/sim
SIM_DIR ?=$(PROJECT_ROOT)/sim
SIM_VLT_DIR ?=$(SIM_DIR)/vlt
SIM_VLT_DIR ?=$(SIM_DIR)/vlt
RTL_SIM_DIR=$(SIM_DIR)
RTL_SIM_DIR=$(SIM_DIR)
RTL_SIM_RUN_DIR=$(RTL_SIM_DIR)/run
RTL_SIM_RUN_DIR=$(RTL_SIM_DIR)/run
RTL_SIM_BIN_DIR=$(RTL_SIM_DIR)/bin
RTL_SIM_BIN_DIR=$(RTL_SIM_DIR)/bin
RTL_SIM_SRC_DIR=$(RTL_SIM_DIR)/src
 
RTL_SIM_RESULTS_DIR=$(RTL_SIM_DIR)/out
RTL_SIM_RESULTS_DIR=$(RTL_SIM_DIR)/out
 
 
# Testbench paths
# Testbench paths
BENCH_DIR=$(PROJECT_ROOT)/bench
BENCH_DIR=$(PROJECT_ROOT)/bench
BENCH_VERILOG_DIR=$(BENCH_DIR)/verilog
BENCH_VERILOG_DIR=$(BENCH_DIR)/verilog
Line 172... Line 171...
#
#
VOPT_ARGS=$(QUIET) -suppress 2241
VOPT_ARGS=$(QUIET) -suppress 2241
# If VCD dump is desired, tell Modelsim not to optimise
# If VCD dump is desired, tell Modelsim not to optimise
# away everything.
# away everything.
ifeq ($(VCD), 1)
ifeq ($(VCD), 1)
#VOPT_ARGS=-voptargs="+acc=rnp"
# If certain versions of modelsim don't have the vopt executable, define
 
# MGC_NO_VOPT=1 when running.
 
ifeq ($(MGC_NO_VOPT), 1)
 
MGC_VSIM_ARGS +=-voptargs="+acc=rnp"
 
MGC_VOPT_CMD=echo
 
MGC_VSIM_TGT=orpsoc_testbench
 
else
 
VOPT_ARGS=+acc=rnpqv
 
MGC_VOPT_CMD= vopt $(QUIET) $(RTL_TESTBENCH_TOP) $(VOPT_ARGS) -o tb
 
MGC_VSIM_TGT=tb
 
endif
 
 
 
else
 
 
 
ifeq ($(MGC_NO_VOPT), 1)
 
MGC_VSIM_ARGS += -vopt
 
MGC_VOPT_CMD=echo
 
MGC_VSIM_TGT=orpsoc_testbench
 
else
VOPT_ARGS=+acc=rnpqv
VOPT_ARGS=+acc=rnpqv
 
MGC_VOPT_CMD= vopt $(QUIET) $(RTL_TESTBENCH_TOP) $(VOPT_ARGS) -o tb
 
MGC_VSIM_TGT=tb
 
endif
 
 
 
 
endif
endif
# VSIM commands
# VSIM commands
# Suppressed warnings - 3009: Failed to open $readmemh() file
# Suppressed warnings - 3009: Failed to open $readmemh() file
# Suppressed warnings - 3009: Module 'blah' does not have a `timescale
# Suppressed warnings - 3009: Module 'blah' does not have a `timescale
#                       directive in effect, but previous modules do.
#                       directive in effect, but previous modules do.
# Suppressed warnings - 8598: Non-positive replication multiplier inside
# Suppressed warnings - 8598: Non-positive replication multiplier inside
#                       concat. Replication will be ignored
#                       concat. Replication will be ignored
MGC_VSIM_ARGS=  -suppress 7 -suppress 3009 -suppress 8598 -c $(QUIET) \
MGC_VSIM_ARGS +=  -suppress 7 -suppress 3009 -suppress 8598 -c $(QUIET) \
                -do "set StdArithNoWarnings 1; run -all; exit"
                -do "set StdArithNoWarnings 1; run -all; exit"
# Options required when VPI option used
# Options required when VPI option used
ifeq ($(VPI), 1)
ifeq ($(VPI), 1)
MGC_VPI_LIB=$(VPI_SRC_C_DIR)/$(MODELTECH_VPILIB)
MGC_VPI_LIB=$(VPI_SRC_C_DIR)/$(MODELTECH_VPILIB)
MGC_VSIM_ARGS += -pli $(VPI_SRC_C_DIR)/$(MODELTECH_VPILIB)
MGC_VSIM_ARGS += -pli $(VPI_SRC_C_DIR)/$(MODELTECH_VPILIB)
Line 281... Line 303...
# Compile script generation rules:
# Compile script generation rules:
 
 
modelsim_dut.scr: rtl $(RTL_VERILOG_SRC) $(RTL_VERILOG_INCLUDES) \
modelsim_dut.scr: rtl $(RTL_VERILOG_SRC) $(RTL_VERILOG_INCLUDES) \
                        $(BOOTROM_VERILOG)
                        $(BOOTROM_VERILOG)
        $(Q)echo "+incdir+"$(RTL_VERILOG_INCLUDE_DIR) > $@;
        $(Q)echo "+incdir+"$(RTL_VERILOG_INCLUDE_DIR) > $@;
        $(Q)echo "+incdir+"$(RTL_SIM_SRC_DIR) >> $@;
 
        $(Q)echo "+incdir+"$(BOOTROM_SW_DIR) >> $@;
        $(Q)echo "+incdir+"$(BOOTROM_SW_DIR) >> $@;
        $(Q)echo "+incdir+"$(BENCH_VERILOG_INCLUDE_DIR) >> $@;
        $(Q)echo "+incdir+"$(BENCH_VERILOG_INCLUDE_DIR) >> $@;
        $(Q)echo "+libext+.v" >> $@;
        $(Q)echo "+libext+.v" >> $@;
        $(Q)for module in $(RTL_VERILOG_MODULES); do \
        $(Q)for module in $(RTL_VERILOG_MODULES); do \
                if [ -d $(RTL_VERILOG_DIR)/$$module ]; then \
                if [ -d $(RTL_VERILOG_DIR)/$$module ]; then \
Line 300... Line 321...
        done
        done
        $(Q)for path in $(BENCH_VERILOG_SRC_SUBDIRS); do \
        $(Q)for path in $(BENCH_VERILOG_SRC_SUBDIRS); do \
                echo "-y "$$path >> $@; \
                echo "-y "$$path >> $@; \
        done
        done
        $(Q)echo "+incdir+"$(RTL_VERILOG_INCLUDE_DIR) >> $@;
        $(Q)echo "+incdir+"$(RTL_VERILOG_INCLUDE_DIR) >> $@;
        $(Q)echo "+incdir+"$(RTL_SIM_SRC_DIR) >> $@;
 
        $(Q)echo "+libext+.v" >> $@;
        $(Q)echo "+libext+.v" >> $@;
        $(Q)echo "-y" $(RTL_SIM_SRC_DIR) >> $@;
 
        $(Q)for vsrc in $(BENCH_VERILOG_SRC); do echo $$vsrc >> $@; done
        $(Q)for vsrc in $(BENCH_VERILOG_SRC); do echo $$vsrc >> $@; done
        $(Q)echo >> $@
        $(Q)echo >> $@
 
 
# Compile DUT into "work" library
# Compile DUT into "work" library
work: modelsim_dut.scr #$(RTL_VHDL_SRC)
work: modelsim_dut.scr #$(RTL_VHDL_SRC)
Line 319... Line 338...
# Single compile rule
# Single compile rule
.PHONY : $(MODELSIM)
.PHONY : $(MODELSIM)
$(MODELSIM): modelsim_bench.scr $(TEST_DEFINES_VLG) $(MGC_VPI_LIB) work
$(MODELSIM): modelsim_bench.scr $(TEST_DEFINES_VLG) $(MGC_VPI_LIB) work
        $(Q)echo; echo "\t### Compiling testbench ###"; echo
        $(Q)echo; echo "\t### Compiling testbench ###"; echo
        $(Q)vlog $(QUIET) -nologo -incr $(BENCH_TOP) -f $<
        $(Q)vlog $(QUIET) -nologo -incr $(BENCH_TOP) -f $<
        $(Q)vopt $(QUIET) $(RTL_TESTBENCH_TOP) $(VOPT_ARGS) -o tb
        $(Q)$(MGC_VOPT_CMD)
        $(Q)echo; echo "\t### Launching simulation ###"; echo
        $(Q)echo; echo "\t### Launching simulation ###"; echo
        $(Q)vsim $(MGC_VSIM_ARGS) tb
        $(Q)vsim $(VOPT_ARGS) $(MGC_VSIM_ARGS) $(MGC_VSIM_TGT)
 
 
#
#
# Icarus Verilog simulator build and run rules
# Icarus Verilog simulator build and run rules
#
#
.PHONY: $(ICARUS_SCRIPT)
.PHONY: $(ICARUS_SCRIPT)
$(ICARUS_SCRIPT):  $(RTL_VERILOG_SRC) $(RTL_VERILOG_INCLUDES) \
$(ICARUS_SCRIPT):  $(RTL_VERILOG_SRC) $(RTL_VERILOG_INCLUDES) \
                $(BOOTROM_VERILOG) $(BENCH_VERILOG_SRC)
                $(BOOTROM_VERILOG) $(BENCH_VERILOG_SRC)
        $(Q)echo "# Icarus Verilog simulation script" > $@
        $(Q)echo "# Icarus Verilog simulation script" > $@
        $(Q)echo "# Auto generated. Any alterations will be written over!" >> $@
        $(Q)echo "# Auto generated. Any alterations will be written over!" >> $@
        $(Q)echo "+incdir+"$(RTL_VERILOG_INCLUDE_DIR) > $@;
        $(Q)echo "+incdir+"$(RTL_VERILOG_INCLUDE_DIR) > $@;
        $(Q)echo "+incdir+"$(RTL_SIM_SRC_DIR) >> $@;
 
        $(Q)echo "+incdir+"$(BENCH_VERILOG_DIR) >> $@;
        $(Q)echo "+incdir+"$(BENCH_VERILOG_DIR) >> $@;
        $(Q)echo "+incdir+"$(BOOTROM_SW_DIR) >> $@;
        $(Q)echo "+incdir+"$(BOOTROM_SW_DIR) >> $@;
        $(Q)for path in $(BENCH_VERILOG_SRC_SUBDIRS); do \
        $(Q)for path in $(BENCH_VERILOG_SRC_SUBDIRS); do \
                echo "+incdir+"$$path >> $@; \
                echo "+incdir+"$$path >> $@; \
        done
        done
Line 344... Line 362...
                echo "-y "$$path >> $@; \
                echo "-y "$$path >> $@; \
        done
        done
        $(Q)for module in $(RTL_VERILOG_MODULES); do \
        $(Q)for module in $(RTL_VERILOG_MODULES); do \
                echo "-y " $(RTL_VERILOG_DIR)/$$module >> $@; \
                echo "-y " $(RTL_VERILOG_DIR)/$$module >> $@; \
        done
        done
        $(Q)echo "-y" $(RTL_SIM_SRC_DIR) >> $@;
 
        $(Q)echo "-y" $(BENCH_VERILOG_DIR) >> $@;
        $(Q)echo "-y" $(BENCH_VERILOG_DIR) >> $@;
        $(Q)echo $(BENCH_TOP) >> $@;
        $(Q)echo $(BENCH_TOP) >> $@;
        $(Q) echo >> $@
        $(Q) echo >> $@
 
 
# Icarus design compilation rule
# Icarus design compilation rule

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