| Line 273... |
Line 273... |
# to do it this way than make them all include a file.
|
# to do it this way than make them all include a file.
|
ifdef USE_SDRAM
|
ifdef USE_SDRAM
|
EVENT_SIM_FLAGS += "-D USE_SDRAM=$(USE_SDRAM)"
|
EVENT_SIM_FLAGS += "-D USE_SDRAM=$(USE_SDRAM)"
|
endif
|
endif
|
|
|
|
|
|
|
# Enable ethernet if defined on the command line
|
# Enable ethernet if defined on the command line
|
ifdef USE_ETHERNET
|
ifdef USE_ETHERNET
|
EVENT_SIM_FLAGS += "-D USE_ETHERNET=$(USE_ETHERNET) -D USE_ETHERNET_IO=$(USE_ETHERNET)"
|
EVENT_SIM_FLAGS += "-D USE_ETHERNET=$(USE_ETHERNET) -D USE_ETHERNET_IO=$(USE_ETHERNET)"
|
# Extra tests we do if ethernet is enabled
|
# Extra tests we do if ethernet is enabled
|
TESTS += eth-basic
|
TESTS += eth-basic eth-int
|
endif
|
endif
|
|
|
SIM_FLASH_MEM_FILE="flash.in"
|
SIM_FLASH_MEM_FILE="flash.in"
|
FLASH_MEM_FILE_SUFFIX="-twobyte-sizefirst.hex"
|
FLASH_MEM_FILE_SUFFIX="-twobyte-sizefirst.hex"
|
SIM_SRAM_MEM_FILE="sram.vmem"
|
SIM_SRAM_MEM_FILE="sram.vmem"
|
| Line 291... |
Line 293... |
|
|
################################################################################
|
################################################################################
|
# Event-driven simulator build rules (Icarus, NCSim)
|
# Event-driven simulator build rules (Icarus, NCSim)
|
################################################################################
|
################################################################################
|
|
|
.PHONY: prepare_rtl
|
$(RTL_VERILOG_DIR)/components/wb_sdram_ctrl/wb_sdram_ctrl_fsm.v:
|
prepare_rtl:
|
|
@cd $(RTL_VERILOG_DIR)/components/wb_sdram_ctrl && perl fizzim.pl -encoding onehot -terse < wb_sdram_ctrl_fsm.fzm > wb_sdram_ctrl_fsm.v
|
@cd $(RTL_VERILOG_DIR)/components/wb_sdram_ctrl && perl fizzim.pl -encoding onehot -terse < wb_sdram_ctrl_fsm.fzm > wb_sdram_ctrl_fsm.v
|
|
$(RTL_VERILOG_DIR)/intercon.v:
|
@cd $(RTL_VERILOG_DIR) && sed '/defparam/!s/\([a-zA-Z0-9_]\)\.//g' intercon.vm > intercon.v
|
@cd $(RTL_VERILOG_DIR) && sed '/defparam/!s/\([a-zA-Z0-9_]\)\.//g' intercon.vm > intercon.v
|
|
|
|
.PHONY: prepare_rtl
|
|
prepare_rtl: $(RTL_VERILOG_DIR)/components/wb_sdram_ctrl/wb_sdram_ctrl_fsm.v $(RTL_VERILOG_DIR)/intercon.v
|
|
|
|
|
ifdef UART_PRINTF
|
ifdef UART_PRINTF
|
TEST_SW_MAKE_OPTS="UART_PRINTF=1"
|
TEST_SW_MAKE_OPTS="UART_PRINTF=1"
|
endif
|
endif
|
|
|
| Line 538... |
Line 543... |
SYSC_LIB_ARCH_DIR=$(shell ls $$SYSTEMC | grep "lib-")
|
SYSC_LIB_ARCH_DIR=$(shell ls $$SYSTEMC | grep "lib-")
|
|
|
|
|
# List of System C models - use this list to link the sources into the Verilator
|
# List of System C models - use this list to link the sources into the Verilator
|
# build directory
|
# build directory
|
SYSC_MODELS=OrpsocAccess
|
SYSC_MODELS=OrpsocAccess MemoryLoad
|
|
|
ifdef VLT_DEBUG
|
ifdef VLT_DEBUG
|
VLT_DEBUG_COMPILE_FLAGS = -g
|
VLT_DEBUG_COMPILE_FLAGS = -g
|
# Enabling the following generates a TON of debugging
|
# Enabling the following generates a TON of debugging
|
# when running verilator. Not so helpful.
|
# when running verilator. Not so helpful.
|
| Line 553... |
Line 558... |
# If set on the command line we build the cycle accurate model which will generate verilator-specific profiling information. This is useful for checking the efficiency of the model - not really useful for checking code or the function of the model.
|
# If set on the command line we build the cycle accurate model which will generate verilator-specific profiling information. This is useful for checking the efficiency of the model - not really useful for checking code or the function of the model.
|
ifdef VLT_ORPSOC_PROFILING
|
ifdef VLT_ORPSOC_PROFILING
|
VLT_CPPFLAGS=-g -pg
|
VLT_CPPFLAGS=-g -pg
|
VLT_DEBUG_OPTIONS +=-profile-cfuncs
|
VLT_DEBUG_OPTIONS +=-profile-cfuncs
|
else
|
else
|
VLT_CPPFLAGS=-fbranch-probabilities -fvpt -funroll-loops -fpeel-loops -ftracer -O3
|
#VLT_CPPFLAGS=-fbranch-probabilities -fvpt -funroll-loops -fpeel-loops -ftracer -O3
|
|
VLT_CPPFLAGS=-Wall
|
endif
|
endif
|
|
|
ifdef VLT_DO_PROFILING
|
ifdef VLT_DO_PROFILING
|
VLT_CPPFLAGS=-O3 -ftest-coverage -fprofile-generate
|
VLT_CPPFLAGS=-O3 -ftest-coverage -fprofile-generate
|
endif
|
endif
|
| Line 582... |
Line 588... |
$(SIM_VLT_DIR)/Vorpsoc_top: $(SIM_VLT_DIR)/libVorpsoc_top.a $(SIM_VLT_DIR)/OrpsocMain.o
|
$(SIM_VLT_DIR)/Vorpsoc_top: $(SIM_VLT_DIR)/libVorpsoc_top.a $(SIM_VLT_DIR)/OrpsocMain.o
|
# Final linking of the simulation executable. Order of libraries here is important!
|
# Final linking of the simulation executable. Order of libraries here is important!
|
@echo; echo "\tGenerating simulation executable"; echo
|
@echo; echo "\tGenerating simulation executable"; echo
|
cd $(SIM_VLT_DIR) && g++ $(VLT_DEBUG_COMPILE_FLAGS) $(VLT_CPPFLAGS) -I$(BENCH_SYSC_INCLUDE_DIR) -I$(SIM_VLT_DIR) -I$(VERILATOR_ROOT)/include -I$(SYSTEMC)/include -o Vorpsoc_top -L. -L$(BENCH_SYSC_SRC_DIR) -L$(SYSTEMC)/$(SYSC_LIB_ARCH_DIR) OrpsocMain.o -lVorpsoc_top -lmodules -lsystemc
|
cd $(SIM_VLT_DIR) && g++ $(VLT_DEBUG_COMPILE_FLAGS) $(VLT_CPPFLAGS) -I$(BENCH_SYSC_INCLUDE_DIR) -I$(SIM_VLT_DIR) -I$(VERILATOR_ROOT)/include -I$(SYSTEMC)/include -o Vorpsoc_top -L. -L$(BENCH_SYSC_SRC_DIR) -L$(SYSTEMC)/$(SYSC_LIB_ARCH_DIR) OrpsocMain.o -lVorpsoc_top -lmodules -lsystemc
|
|
|
$(SIM_VLT_DIR)/OrpsocMain.o:
|
# Now compile the top level systemC "testbench" module from the systemC source path
|
# Now compile the top level systemC "testbench" module
|
$(SIM_VLT_DIR)/OrpsocMain.o: $(BENCH_SYSC_SRC_DIR)/OrpsocMain.cpp
|
@echo; echo "\tCompiling top level SystemC testbench"; echo
|
@echo; echo "\tCompiling top level SystemC testbench"; echo
|
cd $(SIM_VLT_DIR) && g++ $(VLT_DEBUG_COMPILE_FLAGS) $(VLT_CPPFLAGS) $(TRACE_FLAGS) -I$(BENCH_SYSC_INCLUDE_DIR) -I$(SIM_VLT_DIR) -I$(VERILATOR_ROOT)/include -I$(SYSTEMC)/include -c $(BENCH_SYSC_SRC_DIR)/OrpsocMain.cpp
|
cd $(SIM_VLT_DIR) && g++ $(VLT_DEBUG_COMPILE_FLAGS) $(VLT_CPPFLAGS) $(TRACE_FLAGS) -I$(BENCH_SYSC_INCLUDE_DIR) -I$(SIM_VLT_DIR) -I$(VERILATOR_ROOT)/include -I$(SYSTEMC)/include -c $(BENCH_SYSC_SRC_DIR)/OrpsocMain.cpp
|
|
|
$(SIM_VLT_DIR)/libVorpsoc_top.a: $(SIM_VLT_DIR)/Vorpsoc_top__ALL.a vlt_modules_compile $(SIM_VLT_DIR)/verilated.o
|
$(SIM_VLT_DIR)/libVorpsoc_top.a: $(SIM_VLT_DIR)/Vorpsoc_top__ALL.a vlt_modules_compile $(SIM_VLT_DIR)/verilated.o
|
# Now archive all of the libraries from verilator witht he other modules we might have
|
# Now archive all of the libraries from verilator witht he other modules we might have
|
| Line 613... |
Line 619... |
@echo; echo "\tCompiling SystemC models"
|
@echo; echo "\tCompiling SystemC models"
|
@cd $(SIM_VLT_DIR) && \
|
@cd $(SIM_VLT_DIR) && \
|
for SYSCMODEL in $(SYSC_MODELS_BUILD); do \
|
for SYSCMODEL in $(SYSC_MODELS_BUILD); do \
|
echo;echo "\t$$SYSCMODEL"; echo; \
|
echo;echo "\t$$SYSCMODEL"; echo; \
|
export CXXFLAGS=$(VLT_DEBUG_COMPILE_FLAGS); \
|
export CXXFLAGS=$(VLT_DEBUG_COMPILE_FLAGS); \
|
export USER_CPPFLAGS="$(VLT_CPPFLAGS)"; \
|
export USER_CPPFLAGS="$(VLT_CPPFLAGS) -I$(BENCH_SYSC_INCLUDE_DIR)"; \
|
export USER_LDDFLAGS="$(VLT_CPPFLAGS)"; \
|
export USER_LDDFLAGS="$(VLT_CPPFLAGS)"; \
|
$(MAKE) -f Vorpsoc_top.mk $$SYSCMODEL.o; \
|
$(MAKE) -f Vorpsoc_top.mk $$SYSCMODEL.o; \
|
done
|
done
|
|
|
$(SIM_VLT_DIR)/Vorpsoc_top__ALL.a: $(SIM_VLT_DIR)/Vorpsoc_top.mk
|
$(SIM_VLT_DIR)/Vorpsoc_top__ALL.a: $(SIM_VLT_DIR)/Vorpsoc_top.mk
|
| Line 638... |
Line 644... |
@echo; echo "\tCompiling SystemC modules"; echo
|
@echo; echo "\tCompiling SystemC modules"; echo
|
@export VLT_CPPFLAGS="$(VLT_CPPFLAGS)"; \
|
@export VLT_CPPFLAGS="$(VLT_CPPFLAGS)"; \
|
$(MAKE) -C $(BENCH_SYSC_SRC_DIR) -f $(BENCH_SYSC_SRC_DIR)/Modules.make $(VLT_SYSC_DEBUG_DEFINE)
|
$(MAKE) -C $(BENCH_SYSC_SRC_DIR) -f $(BENCH_SYSC_SRC_DIR)/Modules.make $(VLT_SYSC_DEBUG_DEFINE)
|
|
|
|
|
|
ALL_VLOG=$(shell find $(RTL_VERILOG_DIR) -name "*.v")
|
|
|
# Verilator command script
|
# Verilator command script
|
# Generate the compile script to give Verilator
|
# Generate the compile script to give Verilator - make it sensitive to the RTL
|
$(SIM_VLT_DIR)/$(VLT_COMMAND_FILE).generated:
|
$(SIM_VLT_DIR)/$(VLT_COMMAND_FILE).generated: $(ALL_VLOG)
|
@echo; echo "\tGenerating verilator compile script"; echo
|
@echo; echo "\tGenerating verilator compile script"; echo
|
@sed < $(SIM_BIN_DIR)/$(VLT_COMMAND_FILE) > $(SIM_VLT_DIR)/$(VLT_COMMAND_FILE).generated \
|
@sed < $(SIM_BIN_DIR)/$(VLT_COMMAND_FILE) > $(SIM_VLT_DIR)/$(VLT_COMMAND_FILE).generated \
|
-e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)! \
|
-e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)! \
|
-e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)! \
|
-e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)! \
|
-e s!\$$BACKEND_DIR!$(BACKEND_DIR)! \
|
-e s!\$$BACKEND_DIR!$(BACKEND_DIR)! \
|
| Line 762... |
Line 770... |
$(MAKE) -C $(SW_DIR)/$$SWDIR clean; \
|
$(MAKE) -C $(SW_DIR)/$$SWDIR clean; \
|
done
|
done
|
|
|
clean-sim:
|
clean-sim:
|
#backup any profiling output files
|
#backup any profiling output files
|
@if [ -f $(SIM_VLT_DIR)/OrpsocMain.gcda ]; then echo "\tBacking up verilator profiling output"; \
|
@if [ -f $(SIM_VLT_DIR)/OrpsocMain.gcda ]; then echo;echo "\tBacking up verilator profiling output to /tmp"; echo; \
|
cp $(SIM_VLT_DIR)/*.gc* /tmp; \
|
cp $(SIM_VLT_DIR)/*.gc* /tmp; \
|
cp $(BENCH_SYSC_SRC_DIR)/*.gc* /tmp; fi
|
cp $(BENCH_SYSC_SRC_DIR)/*.gc* /tmp; fi
|
rm -rf $(SIM_RESULTS_DIR) $(SIM_RUN_DIR)/*.* $(SIM_VLT_DIR)
|
rm -rf $(SIM_RESULTS_DIR) $(SIM_RUN_DIR)/*.* $(SIM_VLT_DIR)
|
|
|
clean-sysc:
|
clean-sysc:
|
