| Line 46... |
Line 46... |
# Usage:
|
# Usage:
|
#
|
#
|
# make rtl-tests
|
# make rtl-tests
|
#
|
#
|
# Run the software tests in the RTL model of the ORPSoC being
|
# Run the software tests in the RTL model of the ORPSoC being
|
# simulated with an event-driven simulator like Icarus. Also
|
# simulated with an event-driven simulator like Icarus. It's also
|
# possible to use Cadence's Verilog simulators with the
|
# possible to use Modelsim's vsim and Cadence's Verilog simulators.
|
# "rtl-nc-tests" target.
|
|
#
|
#
|
# make vlt-tests
|
# make vlt-tests
|
#
|
#
|
# Run all the software tests in the RTL model which has been
|
# Run all the software tests in the RTL model which has been
|
# converted into a cycle-accurate SystemC model with Verilator.
|
# converted into a cycle-accurate SystemC model with Verilator.
|
| Line 262... |
Line 261... |
ICARUS=iverilog
|
ICARUS=iverilog
|
ICARUS_VVP=vvp
|
ICARUS_VVP=vvp
|
ICARUS_COMMAND_FILE=icarus.scr
|
ICARUS_COMMAND_FILE=icarus.scr
|
VLT_COMMAND_FILE=verilator.scr
|
VLT_COMMAND_FILE=verilator.scr
|
SIM_SUCCESS_MESSAGE=deaddead
|
SIM_SUCCESS_MESSAGE=deaddead
|
|
MGC_COMMAND_FILE=modelsim.scr
|
|
|
ARCH_SIM_EXE=or32-elf-sim
|
ARCH_SIM_EXE=or32-elf-sim
|
ARCH_SIM_CFG_FILE=or1ksim-orpsocv2.cfg
|
ARCH_SIM_CFG_FILE=or1ksim-orpsocv2.cfg
|
|
|
# If USE_SDRAM is defined we'll add it to the simulator's defines on the
|
# If USE_SDRAM is defined we'll add it to the simulator's defines on the
|
| Line 273... |
Line 273... |
# to do it this way than make them all include a file.
|
# to do it this way than make them all include a file.
|
ifdef USE_SDRAM
|
ifdef USE_SDRAM
|
EVENT_SIM_FLAGS += "-D USE_SDRAM=$(USE_SDRAM)"
|
EVENT_SIM_FLAGS += "-D USE_SDRAM=$(USE_SDRAM)"
|
endif
|
endif
|
|
|
|
# Set SIMULATOR=vsim on command line to use Modelsim
|
|
ifeq ($(SIMULATOR), vsim)
|
|
# Modelsim
|
|
SIM_COMMANDFILE=$(MGC_COMMAND_FILE)
|
|
else
|
|
# Icarus Verilog Simulator
|
|
SIM_COMMANDFILE=$(ICARUS_COMMAND_FILE)
|
|
endif
|
|
|
|
GENERATED_COMMANDFILE=$(SIM_COMMANDFILE).generated
|
|
|
|
# When Modelsim is selected as simulator, we compile
|
|
# the ORPSoC system into one library called orpsoc and
|
|
# then simply re-compile the testbench and or1200_monitor
|
|
# whenever we run the simulation, so just that part is
|
|
# recompiled for every test, instead of the whole thing.
|
|
MGC_ORPSOC_LIB=orpsoc
|
|
MGC_ORPSOC_LIB_DIR=$(SIM_RUN_DIR)/$(MGC_ORPSOC_LIB)
|
|
|
|
# If VCD dump is desired, tell Modelsim not to optimise
|
|
# away everything.
|
|
ifeq ($(VCD), 1)
|
|
VOPT_ARGS=-voptargs="+acc=rnp"
|
|
endif
|
|
|
|
# Simulation compile and run commands, depending on your
|
|
# simulator. Currently only Modelsim (vsim) and Icarus right
|
|
# now.
|
|
# TODO: Put the NC-sim commands in here too and have just the
|
|
# single simulation test loop rule.
|
|
ifeq ($(SIMULATOR), vsim)
|
|
# Line to compile the orpsoc design into a modelsim library.
|
|
SIM_COMMANDCOMPILE=if [ ! -e work ]; then vlib work; vlib $(MGC_ORPSOC_LIB); vlog -work orpsoc -f $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE); fi
|
|
# Final modelsim compile, done each time, pulling in or1200
|
|
# monitor and the new test_defines.v file:
|
|
VSIM_COMPILE_TB=vlog +incdir+. +incdir+$(BENCH_VERILOG_DIR) +incdir+$(RTL_VERILOG_DIR) +define+TEST_DEFINE_FILE $(BENCH_VERILOG_DIR)/or1200_monitor.v $(BENCH_VERILOG_DIR)/orpsoc_testbench.v
|
|
# Simulation run command:
|
|
SIM_COMMANDRUN=$(VSIM_COMPILE_TB); vsim -c -quiet +nowarnTFMPC -L $(MGC_ORPSOC_LIB) $(VOPT_ARGS) -do "run -all; exit" orpsoc_testbench
|
|
else
|
|
# Icarus Verilog Simulator compile command
|
|
SIM_COMMANDCOMPILE=rm -f $(SIM_RUN_DIR)/a.out; $(ICARUS) -sorpsoc_testbench -c $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE) $(EVENT_SIM_FLAGS)
|
|
# Icarus Verilog run command
|
|
SIM_COMMANDRUN=$(ICARUS_VVP) -l $(SIM_RESULTS_DIR)/$$TEST-vvp-out.log a.out
|
|
endif
|
|
|
# Enable ethernet if defined on the command line
|
# Enable ethernet if defined on the command line
|
ifdef USE_ETHERNET
|
ifdef USE_ETHERNET
|
EVENT_SIM_FLAGS += "-D USE_ETHERNET=$(USE_ETHERNET) -D USE_ETHERNET_IO=$(USE_ETHERNET)"
|
EVENT_SIM_FLAGS += "-D USE_ETHERNET=$(USE_ETHERNET) -D USE_ETHERNET_IO=$(USE_ETHERNET)"
|
# Extra tests we do if ethernet is enabled
|
# Extra tests we do if ethernet is enabled
|
| Line 295... |
Line 338... |
# Event-driven simulator build rules (Icarus, NCSim)
|
# Event-driven simulator build rules (Icarus, NCSim)
|
################################################################################
|
################################################################################
|
|
|
$(RTL_VERILOG_DIR)/components/wb_sdram_ctrl/wb_sdram_ctrl_fsm.v:
|
$(RTL_VERILOG_DIR)/components/wb_sdram_ctrl/wb_sdram_ctrl_fsm.v:
|
@cd $(RTL_VERILOG_DIR)/components/wb_sdram_ctrl && perl fizzim.pl -encoding onehot -terse < wb_sdram_ctrl_fsm.fzm > wb_sdram_ctrl_fsm.v
|
@cd $(RTL_VERILOG_DIR)/components/wb_sdram_ctrl && perl fizzim.pl -encoding onehot -terse < wb_sdram_ctrl_fsm.fzm > wb_sdram_ctrl_fsm.v
|
$(RTL_VERILOG_DIR)/intercon.v:
|
|
@cd $(RTL_VERILOG_DIR) && sed '/defparam/!s/\([a-zA-Z0-9_]\)\.//g' intercon.vm > intercon.v
|
|
|
|
.PHONY: prepare_rtl
|
.PHONY: prepare_rtl
|
prepare_rtl: $(RTL_VERILOG_DIR)/components/wb_sdram_ctrl/wb_sdram_ctrl_fsm.v #$(RTL_VERILOG_DIR)/intercon.v
|
prepare_rtl: $(RTL_VERILOG_DIR)/components/wb_sdram_ctrl/wb_sdram_ctrl_fsm.v
|
|
|
|
$(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE): $(SIM_BIN_DIR)/$(SIM_COMMANDFILE)
|
|
@sed < $(SIM_BIN_DIR)/$(SIM_COMMANDFILE) > $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE) \
|
|
-e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)! \
|
|
-e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)! \
|
|
-e s!\$$BACKEND_DIR!$(BACKEND_DIR)! \
|
|
-e \\!^//.*\$$!d -e \\!^\$$!d ; \
|
|
echo "+define+TEST_DEFINE_FILE=\"test_define.v\"" >> $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE); \
|
|
if [ ! -z $$VCD ]; \
|
|
then echo "+define+VCD" >> $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE); \
|
|
fi; \
|
|
if [ ! -z $$UART_PRINTF ]; \
|
|
then echo "+define+UART_PRINTF" >> $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE); \
|
|
fi
|
|
|
ifdef UART_PRINTF
|
ifdef UART_PRINTF
|
TEST_SW_MAKE_OPTS="UART_PRINTF=1"
|
TEST_SW_MAKE_OPTS="UART_PRINTF=1"
|
endif
|
endif
|
|
|
| Line 319... |
Line 373... |
@$(MAKE) -C $(SW_DIR)/utils all
|
@$(MAKE) -C $(SW_DIR)/utils all
|
|
|
prepare_dirs:
|
prepare_dirs:
|
@if [ ! -d $(SIM_RESULTS_DIR) ]; then mkdir -p $(SIM_RESULTS_DIR); fi
|
@if [ ! -d $(SIM_RESULTS_DIR) ]; then mkdir -p $(SIM_RESULTS_DIR); fi
|
|
|
# Rough guide to how these tests work:
|
#
|
# First, the couple of custom, required, software tools under sw/utils are
|
# Rough guide to how event driven simulation test loop works:
|
# compiled, and then the software library files.
|
#
|
# Next the few verilog files that need preperation are taken care of.
|
# 1. Compile software support programs.
|
# The test begins by starting a loop in bash using on the strings defined in
|
# 2. Generate RTL compilation script file
|
# TESTS. Each one corresponds to a certain module of software for the OpenRISC
|
# 3. For each test listed in $(TESTS), loop and
|
# that is included in this test suite. Under the sw/ path is a set of paths,
|
# a) Compile software
|
# and all except the support/ and utils/ paths contain code which is run to
|
# b) Create appropriate image to be loaded into sim
|
# test the OR1k used in this test suite. For each of these software modules,
|
# c) Create a verilog file to be included by top level
|
# it is possible that different tests are done using the same module. These
|
# d) Compile the RTL design
|
# tests can vary by either using different levels of optimisation during
|
# e) Run the RTL design in the chosen simulator
|
# compilation, and/or by having the OR1k's caches enabled or disabled.
|
# f) Check the output (files in ../results)
|
# Each test has a unique name, and under the $(SIM_RESULTS_DIR), which is
|
#
|
# usually just ../results, log files, and optionally VCD files, are created for
|
# Default setup is:
|
# inspection later and are named according to the test. Inspect the file
|
# * Event-driven simulation with Icarus Verilog
|
# bench/verilog/or1200_monitor.v to find out in detail what each log consists
|
# * Internal SRAM memory, preloaded with application
|
# of.
|
# * Ethernet disabled
|
# For each test, a few things occur. First the software that will run inside
|
# * VCD generation disabled
|
# the simulated OR1k system is compiled, converted to a format which can be
|
# * printf() via UART disabled
|
# read
|
# * Logging enabled
|
# into the flash memory model via $readmemh() and linked to the sim/run
|
#
|
# directory as $(SIM_FLASH_MEM_FILE), which currently is flash.in. Next a
|
# Options:
|
# compilation script for icarus is generated, containing a list of all the
|
# SIMULATOR=vsim
|
# RTL files and include directories. Next, an include file for the verilog
|
# Use Mentor Graphics Modelsim simulator
|
# testbench is generated, containing a string of the name of the current
|
# USE_SDRAM=1
|
# test, path to the results directory (for VCD generation) and any other
|
# Enable use of SDRAM - changes boot sequence and takes
|
# things which might vary from test to test. This is not done by +define
|
# a lot longer due to application being loaded out of
|
# lines in the icarus script because of string handling incosistencies
|
# external FLASH memory and into SDRAM before execution
|
# between different simulators and shells.
|
# from the SDRAM.
|
# Once all the files are generated, icarus is called to compile the rtl
|
# VCD=1
|
# design, and then run it. Each of the tested software modules have code which
|
# Enable VCD generation. These files are output to
|
# will trigger the simulation to be stopped by use of the l.nop instruction
|
# ../results
|
# with an immediate value of 1. When the simulation finishes, the simulation
|
# USE_ETHERNET=1
|
# executable exits and the log of the simulation is inspected for the expected
|
# Turns on ethernet core inclusion. There are currently
|
# output. Currently, the string "deaddead" indicates that the software
|
# some tests, but not included by default. Check the sw
|
# completed successfully. This is counted as the ORPSoC "passing" the test. In
|
# directory
|
# fact, whether the system did the right thing or not requires more
|
# UART_PRINTF=1
|
# inspection, but roughly this is a good indicator that nothing major went
|
# Make the software use the UART core to print out
|
# wrong.
|
# printf() calls.
|
# Once the current test is finished, the next begins with the compilation of its
|
# NO_SIM_LOGGING=1
|
# software and linking of the resulting hex file to the run path, etc.
|
# Turn off generation of logging files in the ../results
|
# Main RAM setup - (RTL simulation with Icarus/NCSim only!):
|
# directory.
|
# Define USE_SDRAM to enable the external SDRAM, otherwise the simulation
|
#
|
# defaults to an internal SRAM. Eg. $ make rtl-tests USE_SDRAM=1 VCD=1
|
rtl-tests: $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE) prepare_sw prepare_rtl prepare_dirs
|
# Verilator defaults to internal memories
|
|
rtl-tests: prepare_sw prepare_rtl prepare_dirs
|
|
@echo
|
@echo
|
@echo "Beginning loop that will complete the following tests: $(TESTS)"
|
@echo "Beginning loop that will complete the following tests: $(TESTS)"
|
@echo
|
@echo
|
@for TEST in $(TESTS); do \
|
@for TEST in $(TESTS); do \
|
echo "################################################################################"; \
|
echo "################################################################################"; \
|
| Line 379... |
Line 431... |
$(MAKE) -C $$CURRENT_TEST_SW_DIR $$TEST $(TEST_SW_MAKE_OPTS); \
|
$(MAKE) -C $$CURRENT_TEST_SW_DIR $$TEST $(TEST_SW_MAKE_OPTS); \
|
rm -f $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \
|
rm -f $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \
|
rm -f $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
|
rm -f $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
|
ln -s $$CURRENT_TEST_SW_DIR/$$TEST$(FLASH_MEM_FILE_SUFFIX) $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \
|
ln -s $$CURRENT_TEST_SW_DIR/$$TEST$(FLASH_MEM_FILE_SUFFIX) $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \
|
ln -s $$CURRENT_TEST_SW_DIR/$$TEST.vmem $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
|
ln -s $$CURRENT_TEST_SW_DIR/$$TEST.vmem $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
|
sed < $(SIM_BIN_DIR)/$(ICARUS_COMMAND_FILE) > $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated \
|
echo "\`define TEST_NAME_STRING \"$$TEST\"" > $(SIM_RUN_DIR)/test_define.v; \
|
-e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)! \
|
echo "\`define TEST_RESULTS_DIR \"$(SIM_RESULTS_DIR)/\" " >> $(SIM_RUN_DIR)/test_define.v; \
|
-e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)! \
|
|
-e s!\$$BACKEND_DIR!$(BACKEND_DIR)! \
|
|
-e \\!^//.*\$$!d -e \\!^\$$!d ; \
|
|
echo "+define+TEST_DEFINE_FILE=\"test_define.v\"" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
|
|
if [ ! -z $$VCD ]; \
|
if [ ! -z $$VCD ]; \
|
then echo "+define+VCD" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
|
then echo "\`define VCD" >> $(SIM_RUN_DIR)/test_define.v; \
|
fi; \
|
fi; \
|
if [ ! -z $$UART_PRINTF ]; \
|
if [ ! -z $$UART_PRINTF ]; \
|
then echo "+define+UART_PRINTF" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
|
then echo "\`define UART_PRINTF" >> $(SIM_RUN_DIR)/test_define.v; \
|
fi; \
|
fi; \
|
echo "\`define TEST_NAME_STRING \"$$TEST\"" > $(SIM_RUN_DIR)/test_define.v; \
|
|
echo "\`define TEST_RESULTS_DIR \"$(SIM_RESULTS_DIR)/\" " >> $(SIM_RUN_DIR)/test_define.v; \
|
|
if echo $$TEST | grep -q -i ^eth; then \
|
if echo $$TEST | grep -q -i ^eth; then \
|
echo "\`define ENABLE_ETH_STIM" >> $(SIM_RUN_DIR)/test_define.v; \
|
echo "\`define ENABLE_ETH_STIM" >> $(SIM_RUN_DIR)/test_define.v; \
|
echo "\`define ETH_PHY_VERBOSE" >> $(SIM_RUN_DIR)/test_define.v; \
|
echo "\`define ETH_PHY_VERBOSE" >> $(SIM_RUN_DIR)/test_define.v; \
|
fi; \
|
fi; \
|
if [ -z $$NO_SIM_LOGGING ]; then \
|
if [ -z $$NO_SIM_LOGGING ]; then \
|
echo "\`define OR1200_DISPLAY_ARCH_STATE" >> $(SIM_RUN_DIR)/test_define.v; \
|
echo "\`define OR1200_DISPLAY_ARCH_STATE" >> $(SIM_RUN_DIR)/test_define.v; \
|
fi; \
|
fi; \
|
echo ; \
|
echo ; \
|
echo "\t#### Compiling RTL ####"; \
|
echo "\t#### Compiling RTL ####"; \
|
rm -f $(SIM_RUN_DIR)/a.out; \
|
$(SIM_COMMANDCOMPILE); \
|
$(ICARUS) -sorpsoc_testbench -c $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated $(EVENT_SIM_FLAGS); \
|
|
echo; \
|
echo; \
|
echo "\t#### Beginning simulation ####"; \
|
echo "\t#### Beginning simulation ####"; \
|
time -p $(ICARUS_VVP) -l $(SIM_RESULTS_DIR)/$$TEST-vvp-out.log a.out ; \
|
time -p $(SIM_COMMANDRUN) ; \
|
if [ $$? -gt 0 ]; then exit $$?; fi; \
|
if [ $$? -gt 0 ]; then exit $$?; fi; \
|
TEST_RESULT=`cat $(SIM_RESULTS_DIR)/$$TEST-general.log | grep report | grep $(SIM_SUCCESS_MESSAGE) -c`; \
|
TEST_RESULT=`cat $(SIM_RESULTS_DIR)/$$TEST-general.log | grep report | grep $(SIM_SUCCESS_MESSAGE) -c`; \
|
echo; echo "\t####"; \
|
echo; echo "\t####"; \
|
if [ $$TEST_RESULT -gt 0 ]; then \
|
if [ $$TEST_RESULT -gt 0 ]; then \
|
echo "\t#### Test $$TEST PASSED ####";TESTS_PASSED=`expr $$TESTS_PASSED + 1`;\
|
echo "\t#### Test $$TEST PASSED ####";TESTS_PASSED=`expr $$TESTS_PASSED + 1`;\
|
| Line 777... |
Line 822... |
clean-sim:
|
clean-sim:
|
#backup any profiling output files
|
#backup any profiling output files
|
@if [ -f $(SIM_VLT_DIR)/OrpsocMain.gcda ]; then echo;echo "\tBacking up verilator profiling output to /tmp"; echo; \
|
@if [ -f $(SIM_VLT_DIR)/OrpsocMain.gcda ]; then echo;echo "\tBacking up verilator profiling output to /tmp"; echo; \
|
cp $(SIM_VLT_DIR)/*.gc* /tmp; \
|
cp $(SIM_VLT_DIR)/*.gc* /tmp; \
|
cp $(BENCH_SYSC_SRC_DIR)/*.gc* /tmp; fi
|
cp $(BENCH_SYSC_SRC_DIR)/*.gc* /tmp; fi
|
rm -rf $(SIM_RESULTS_DIR) $(SIM_RUN_DIR)/*.* $(SIM_VLT_DIR)
|
rm -rf $(SIM_RESULTS_DIR) $(SIM_RUN_DIR)/*.* $(SIM_VLT_DIR) $(MGC_ORPSOC_LIB_DIR) $(SIM_RUN_DIR)/work $(SIM_RUN_DIR)/transcript
|
|
|
clean-sysc:
|
clean-sysc:
|
# Clean away dependency files generated by verilator
|
# Clean away dependency files generated by verilator
|
$(MAKE) -C $(BENCH_SYSC_SRC_DIR) -f $(BENCH_SYSC_SRC_DIR)/Modules.make clean
|
$(MAKE) -C $(BENCH_SYSC_SRC_DIR) -f $(BENCH_SYSC_SRC_DIR)/Modules.make clean
|
|
|
clean-rtl:
|
clean-rtl:
|
# Clean away temporary verilog source files
|
# Clean away temporary verilog source files
|
rm -f $(RTL_VERILOG_DIR)/intercon.v
|
|
rm -f $(RTL_VERILOG_DIR)/components/wb_sdram_ctrl/wb_sdram_ctrl_fsm.v
|
rm -f $(RTL_VERILOG_DIR)/components/wb_sdram_ctrl/wb_sdram_ctrl_fsm.v
|
|
|
