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clean-sim-test-sw:
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clean-sim-test-sw:
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$(Q)if [ -e $(SIM_SW_IMAGE) ]; then unlink $(SIM_SW_IMAGE); fi
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$(Q)if [ -e $(SIM_SW_IMAGE) ]; then unlink $(SIM_SW_IMAGE); fi
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clean-sw:
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clean-sw:
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$(Q) echo; echo "\t### Cleaning simulation sw directories ###"; echo;
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$(Q) echo; echo "\t### Cleaning simulation sw directories ###"; echo;
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$(Q) $(MAKE) -C $(SW_DIR)/lib clean-all
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$(Q) $(MAKE) -C $(SW_DIR)/lib distclean
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clean-rtl:
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clean-rtl:
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$(Q) echo; echo "\t### Cleaning generated verilog RTL ###"; echo;
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$(Q) echo; echo "\t### Cleaning generated verilog RTL ###"; echo;
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for module in $(RTL_TO_CHECK); do \
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for module in $(RTL_TO_CHECK); do \
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$(MAKE) -C $(RTL_VERILOG_DIR)/$$module clean; \
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$(MAKE) -C $(RTL_VERILOG_DIR)/$$module clean; \
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