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Line 235... |
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# Name of the directory we're currently in
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# Name of the directory we're currently in
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CUR_DIR=$(shell pwd)
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CUR_DIR=$(shell pwd)
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# The root path of the whole project
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# The root path of the whole project
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PROJECT_ROOT=$(CUR_DIR)/../..
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PROJECT_ROOT ?=$(CUR_DIR)/../..
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# Tests is only defined if it wasn't already defined when make was called
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# Tests is only defined if it wasn't already defined when make was called
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# This is the default list of every test that is currently possible
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# This is the default list of every test that is currently possible
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TESTS ?= basic-nocache cbasic-nocache-O2 dhry-nocache-O2 except-nocache mmu-nocache mul-nocache-O2 syscall-nocache tick-nocache uart-nocache basic-icdc cbasic-icdc-O2 dhry-icdc-O2 except-icdc mmu-icdc mul-icdc-O2 syscall-icdc tick-icdc uart-icdc
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TESTS ?= basic-nocache cbasic-nocache-O2 dhry-nocache-O2 except-nocache mmu-nocache mul-nocache-O2 syscall-nocache tick-nocache uart-nocache basic-icdc cbasic-icdc-O2 dhry-icdc-O2 except-icdc mmu-icdc mul-icdc-O2 syscall-icdc tick-icdc uart-icdc
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# Paths to other important parts of this test suite
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# Paths to other important parts of this test suite
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SIM_DIR=$(PROJECT_ROOT)/sim
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SIM_DIR ?=$(PROJECT_ROOT)/sim
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SIM_RUN_DIR=$(SIM_DIR)/run
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SIM_RUN_DIR=$(SIM_DIR)/run
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SIM_BIN_DIR=$(SIM_DIR)/bin
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SIM_BIN_DIR=$(SIM_DIR)/bin
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SIM_RESULTS_DIR=$(SIM_DIR)/results
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SIM_RESULTS_DIR=$(SIM_DIR)/results
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SIM_VLT_DIR=$(SIM_DIR)/vlt
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SIM_VLT_DIR=$(SIM_DIR)/vlt
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BENCH_DIR=$(PROJECT_ROOT)/bench
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BENCH_DIR=$(PROJECT_ROOT)/bench
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BACKEND_DIR=$(PROJECT_ROOT)/backend
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BACKEND_DIR ?=$(PROJECT_ROOT)/backend
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BENCH_VERILOG_DIR=$(BENCH_DIR)/verilog
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BENCH_VERILOG_DIR=$(BENCH_DIR)/verilog
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BENCH_TOP_VERILOG_DIR ?= $(BENCH_DIR)/verilog
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BENCH_SYSC_DIR=$(BENCH_DIR)/sysc
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BENCH_SYSC_DIR=$(BENCH_DIR)/sysc
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BENCH_SYSC_SRC_DIR=$(BENCH_SYSC_DIR)/src
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BENCH_SYSC_SRC_DIR=$(BENCH_SYSC_DIR)/src
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BENCH_SYSC_INCLUDE_DIR=$(BENCH_SYSC_DIR)/include
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BENCH_SYSC_INCLUDE_DIR=$(BENCH_SYSC_DIR)/include
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RTL_VERILOG_DIR=$(PROJECT_ROOT)/rtl/verilog
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RTL_VERILOG_DIR=$(PROJECT_ROOT)/rtl/verilog
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SW_DIR=$(PROJECT_ROOT)/sw
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SW_DIR=$(PROJECT_ROOT)/sw
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| Line 328... |
Line 329... |
# away everything.
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# away everything.
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ifeq ($(VCD), 1)
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ifeq ($(VCD), 1)
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VOPT_ARGS=-voptargs="+acc=rnp"
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VOPT_ARGS=-voptargs="+acc=rnp"
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endif
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endif
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# RTL testbench toplevel name
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RTL_TESTBENCH_TOP ?= orpsoc_testbench
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# Simulation compile and run commands, depending on your
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# Simulation compile and run commands, depending on your
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# simulator.
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# simulator.
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# Icarus Verilog
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# Icarus Verilog
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ifeq ($(SIMULATOR), $(ICARUS))
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ifeq ($(SIMULATOR), $(ICARUS))
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# Icarus Verilog Simulator compile and run commands
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# Icarus Verilog Simulator compile and run commands
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SIM_COMMANDCOMPILE=rm -f $(SIM_RUN_DIR)/a.out; $(ICARUS) -sorpsoc_testbench -c $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE) $(EVENT_SIM_FLAGS)
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SIM_COMMANDCOMPILE=rm -f $(SIM_RUN_DIR)/a.out; $(ICARUS) -s$(RTL_TESTBENCH_TOP) -c $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE) $(EVENT_SIM_FLAGS)
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# Icarus Verilog run command
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# Icarus Verilog run command
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SIM_COMMANDRUN=$(ICARUS_VVP) -l $(SIM_RESULTS_DIR)/$$TEST-vvp-out.log a.out
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SIM_COMMANDRUN=$(ICARUS_VVP) -l $(SIM_RESULTS_DIR)/$$TEST-vvp-out.log a.out
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endif
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endif
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# Modelsim
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# Modelsim
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ifeq ($(SIMULATOR), $(VSIM))
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ifeq ($(SIMULATOR), $(VSIM))
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# Line to compile the orpsoc design into a modelsim library.
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# Line to compile the orpsoc design into a modelsim library.
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SIM_COMMANDCOMPILE=if [ ! -e work ]; then vlib work; vlib $(MGC_ORPSOC_LIB); vlog -work orpsoc -f $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE); fi
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SIM_COMMANDCOMPILE=if [ ! -e work ]; then vlib work; vlib $(MGC_ORPSOC_LIB); vlog -work $(MGC_ORPSOC_LIB) -f $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE); fi
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# Final modelsim compile, done each time, pulling in or1200
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# Final modelsim compile, done each time, pulling in or1200
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# monitor and the new test_defines.v file:
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# monitor and the new test_defines.v file:
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VSIM_COMPILE_TB=vlog +incdir+. +incdir+$(BENCH_VERILOG_DIR) +incdir+$(RTL_VERILOG_DIR) +define+TEST_DEFINE_FILE $(BENCH_VERILOG_DIR)/or1200_monitor.v $(BENCH_VERILOG_DIR)/orpsoc_testbench.v
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VSIM_COMPILE_TB=vlog +incdir+. +incdir+$(BENCH_VERILOG_DIR) +incdir+$(BENCH_TOP_VERILOG_DIR) +incdir+$(RTL_VERILOG_DIR) +define+TEST_DEFINE_FILE $(BENCH_VERILOG_DIR)/or1200_monitor.v $(BENCH_TOP_VERILOG_DIR)/$(RTL_TESTBENCH_TOP).v
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# Simulation run command:
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# Simulation run command:
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SIM_COMMANDRUN=$(VSIM_COMPILE_TB); $(VSIM) -c -quiet +nowarnTFMPC -L $(MGC_ORPSOC_LIB) $(VOPT_ARGS) -do "run -all; exit" orpsoc_testbench
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SIM_COMMANDRUN=$(VSIM_COMPILE_TB); $(VSIM) -c -quiet +nowarnTFMPC -L $(MGC_ORPSOC_LIB) $(VOPT_ARGS) -do "run -all; exit" $(RTL_TESTBENCH_TOP)
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endif
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endif
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# NCVerilog
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# NCVerilog
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ifeq ($(SIMULATOR), $(NCVERILOG))
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ifeq ($(SIMULATOR), $(NCVERILOG))
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SIM_COMMANDCOMPILE=echo
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SIM_COMMANDCOMPILE=echo
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| Line 554... |
Line 558... |
$(Q)echo "\`define TEST_RESULTS_DIR \"$(SIM_RESULTS_DIR)/\" " >> $(SIM_RUN_DIR)/test_define.v
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$(Q)echo "\`define TEST_RESULTS_DIR \"$(SIM_RESULTS_DIR)/\" " >> $(SIM_RUN_DIR)/test_define.v
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$(Q)if [ -z $$NO_SIM_LOGGING ]; then echo "\`define OR1200_DISPLAY_ARCH_STATE" >> $(SIM_RUN_DIR)/test_define.v; fi
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$(Q)if [ -z $$NO_SIM_LOGGING ]; then echo "\`define OR1200_DISPLAY_ARCH_STATE" >> $(SIM_RUN_DIR)/test_define.v; fi
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@echo
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@echo
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@echo "\t#### Compiling RTL ####"
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@echo "\t#### Compiling RTL ####"
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$(Q)rm -f $(SIM_RUN_DIR)/a.out
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$(Q)rm -f $(SIM_RUN_DIR)/a.out
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$(Q)$(ICARUS) -sorpsoc_testbench -c $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated $(EVENT_SIM_FLAGS)
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$(Q)$(ICARUS) -s$(RTL_TESTBENCH_TOP) -c $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated $(EVENT_SIM_FLAGS)
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@echo
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@echo
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@echo "\t#### Beginning simulation with VPI debug module enabled ####"; echo
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@echo "\t#### Beginning simulation with VPI debug module enabled ####"; echo
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$(Q)$(ICARUS_VVP) $(ICARUS_VPI_OPTS) -l $(SIM_RESULTS_DIR)/$(VPI_TEST_SW)-vvp-out.log a.out
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$(Q)$(ICARUS_VVP) $(ICARUS_VPI_OPTS) -l $(SIM_RESULTS_DIR)/$(VPI_TEST_SW)-vvp-out.log a.out
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################################################################################
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################################################################################
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