OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [Makefile.inc] - Diff between revs 392 and 393

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 392 Rev 393
Line 93... Line 93...
                $(DRIVER_INCLUDE_PATHS) \
                $(DRIVER_INCLUDE_PATHS) \
                -I$(SW_ROOT)/lib/include
                -I$(SW_ROOT)/lib/include
 
 
OR32_LDFLAGS ?=-lgcc -T$(CPU_DRIVER)/link.ld -e 256
OR32_LDFLAGS ?=-lgcc -T$(CPU_DRIVER)/link.ld -e 256
OR32_ARFLAGS ?=-r
OR32_ARFLAGS ?=-r
# RTL_VERILOG_INCLUDE_PATH _MUST_ be set!
# RTL_VERILOG_INCLUDE_DIR *MUST* be set!
# Backup one - default, but may be wrong!
# Backup one - default, but may be wrong!
RTL_VERILOG_INCLUDE_PATH ?= $(SW_ROOT)/../rtl/verilog/include
RTL_VERILOG_INCLUDE_DIR ?= $(SW_ROOT)/../rtl/verilog/include
 
 
DESIGN_VERILOG_DEFINES=$(RTL_VERILOG_INCLUDE_PATH)/$(DESIGN_NAME)-defines.v
DESIGN_VERILOG_DEFINES=$(RTL_VERILOG_INCLUDE_DIR)/$(DESIGN_NAME)-defines.v
DESIGN_PROCESSED_VERILOG_DEFINES=$(SW_ROOT)/lib/include/$(DESIGN_NAME)-defines.h
DESIGN_PROCESSED_VERILOG_DEFINES=$(SW_ROOT)/lib/include/$(DESIGN_NAME)-defines.h
 
 
OR1200_VERILOG_DEFINES=$(RTL_VERILOG_INCLUDE_PATH)/or1200_defines.v
OR1200_VERILOG_DEFINES=$(RTL_VERILOG_INCLUDE_DIR)/or1200_defines.v
OR1200_PROCESSED_VERILOG_DEFINES=$(SW_ROOT)/lib/include/or1200-defines.h
OR1200_PROCESSED_VERILOG_DEFINES=$(SW_ROOT)/lib/include/or1200-defines.h
 
 
PROCESSED_DEFINES=$(DESIGN_PROCESSED_VERILOG_DEFINES) $(OR1200_PROCESSED_VERILOG_DEFINES)
PROCESSED_DEFINES=$(DESIGN_PROCESSED_VERILOG_DEFINES) $(OR1200_PROCESSED_VERILOG_DEFINES)
 
 
ELF_DEPENDS+= $(SUPPORT_LIBS) $(VECTORS_OBJ)
ELF_DEPENDS+= $(SUPPORT_LIBS)
 
 
# Set V=1 when calling make to enable verbose output
# Set V=1 when calling make to enable verbose output
# mainly for debugging purposes.
# mainly for debugging purposes.
ifeq ($(V), 1)
ifeq ($(V), 1)
Q=
Q=
Line 153... Line 153...
        $(Q)$(UTILS_BIN2HEX) $< 1  -size_word > $@
        $(Q)$(UTILS_BIN2HEX) $< 1  -size_word > $@
 
 
%.vmem: %.bin $(UTILS_BIN2VMEM)
%.vmem: %.bin $(UTILS_BIN2VMEM)
        $(Q)$(UTILS_BIN2VMEM) $< > $@
        $(Q)$(UTILS_BIN2VMEM) $< > $@
 
 
%.elf: %.c $(ELF_DEPENDS)
%.elf: %.c $(ELF_DEPENDS) $(VECTORS_OBJ)
        $(Q)$(OR32_CC) $^ $(OR32_CFLAGS) $(OR32_LDFLAGS) -o $@
        $(Q)$(OR32_CC) $^ $(OR32_CFLAGS) $(OR32_LDFLAGS) -o $@
 
 
%.elf: %.S $(ELF_DEPENDS)
%.elf: %.S $(ELF_DEPENDS)
        $(Q)$(OR32_CC) $^ $(OR32_CFLAGS) $(OR32_LDFLAGS) -o $@
        $(Q)$(OR32_CC) $^ $(OR32_CFLAGS) $(OR32_LDFLAGS) -o $@
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.