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URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [bootrom/] [bootrom.S] - Diff between revs 403 and 415

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Rev 403 Rev 415
Line 40... Line 40...
#include "board.h"
#include "board.h"
 
 
#ifdef BOOTROM_SPI_FLASH
#ifdef BOOTROM_SPI_FLASH
 
 
        /* Assembly program to go into the boot ROM */
        /* Assembly program to go into the boot ROM */
 
        /* For use with simple_spi SPI master core and standard SPI flash
 
           interface-compatible parts (ST M25P16 for example.)*/
        /* Currently just loads a program from SPI flash into RAM */
        /* Currently just loads a program from SPI flash into RAM */
        /* Assuming address at RAM_LOAD_BASE gets clobbered, we need
        /* Assuming address at RAM_LOAD_BASE gets clobbered, we need
           a byte writable address somewhere!*/
           a byte writable address somewhere!*/
 
 
#define SPI_BASE SPI0_BASE
#define SPI_BASE SPI0_BASE
Line 69... Line 71...
spi_init:
spi_init:
        l.ori r2, r0, SPI_SPCR_XFER_GO /* Setup SPCR with enable bit set */
        l.ori r2, r0, SPI_SPCR_XFER_GO /* Setup SPCR with enable bit set */
        l.sb SPI_SPCR(r4), r2
        l.sb SPI_SPCR(r4), r2
        l.sb  SPI_SPSS(r4), r0         /* Clear SPI slave selects */
        l.sb  SPI_SPSS(r4), r0         /* Clear SPI slave selects */
        l.ori r6, r0, SPI_SPSS_INIT
        l.ori r6, r0, SPI_SPSS_INIT
        l.sb  SPI_SPSS(r4), r6         /* Now put in appropriate slave select */
        l.sb    SPI_SPSS(r4), r6         /* Set appropriate slave select */
        l.jal spi_xfer
        l.jal spi_xfer
        l.ori r3, r0, 0x3              /* READ command opcode for SPI device */
        l.ori r3, r0, 0x3              /* READ command opcode for SPI device */
        l.jal spi_xfer
        l.jal spi_xfer
 
#ifdef BOOTROM_ADDR_BYTE2
 
        l.ori   r3, r0, BOOTROM_ADDR_BYTE2 /* Use addr if defined. MSB first */
 
#else
        l.or r3, r0, r0
        l.or r3, r0, r0
 
#endif
        l.jal spi_xfer
        l.jal spi_xfer
 
#ifdef BOOTROM_ADDR_BYTE1
 
        l.ori   r3, r0, BOOTROM_ADDR_BYTE1
 
#else
        l.or r3, r0, r0
        l.or r3, r0, r0
 
#endif
        l.jal spi_xfer
        l.jal spi_xfer
 
#ifdef BOOTROM_ADDR_BYTE0
 
        l.ori   r3, r0, BOOTROM_ADDR_BYTE0
 
#else
        l.or r3, r0, r0
        l.or r3, r0, r0
 
#endif
        l.movhi r6, 0
        l.movhi r6, 0
        l.movhi r7, 0xffff
        l.movhi r7, 0xffff
 
 
copy:
copy:
        l.jal spi_xfer         /* Read a byte into r3 */
        l.jal spi_xfer         /* Read a byte into r3 */
        l.add r8, r1, r6       /* Calculate store address */
        l.add r8, r1, r6       /* Calculate store address */
        l.sb 0(r8), r3         /* Write byte to memory */
        l.sb 0(r8), r3         /* Write byte to memory */
        l.addi r6, r6, 1       /* Increment counter */
        l.addi r6, r6, 1       /* Increment counter */
        l.sfeqi r6, 0x4        /* Is this the first word */
        l.sfeqi r6, 0x4          /* Is this the first word ?*/
        l.bf store_sizeword    /* put sizeword in the register */
        l.bf store_sizeword    /* put sizeword in the register */
        l.sfeq r6, r7          /* Check if we've finished loading the words */
        l.sfeq r6, r7          /* Check if we've finished loading the words */
        l.bnf copy             /* Continue copying if not last word */
        l.bnf copy             /* Continue copying if not last word */
        l.nop
        l.nop
 
 
Line 98... Line 112...
        l.ori r1, r1, RESET_ADDR
        l.ori r1, r1, RESET_ADDR
        l.jr r1
        l.jr r1
        l.sb  SPI_SPSS(r4), r0 /* Clear SPI slave selects */
        l.sb  SPI_SPSS(r4), r0 /* Clear SPI slave selects */
 
 
store_sizeword:
store_sizeword:
 
#ifdef SPI_RETRY_IF_INSANE_SIZEWORD
 
        l.lwz   r7, 0(r1)        /* Size word is in first word of SDRAM */
 
        l.srli  r10, r7, 16      /* Chop the sizeword we read in half */
 
        l.sfgtui r10, 0x0200     /* It's unlikely we'll ever load > 32MB */
 
        l.bf    boot_init
 
        l.nop
 
        l.j     copy
 
        l.nop
 
 
 
#else
        l.j copy
        l.j copy
        l.lwz r7, 0(r1)         /* Size word is in first word of SDRAM */
        l.lwz r7, 0(r1)         /* Size word is in first word of SDRAM */
 
#endif
 
 
spi_xfer:
spi_xfer:
        l.sb SPI_SPDR(r4), r3  /* Dummy write what's in r3 */
        l.sb SPI_SPDR(r4), r3  /* Dummy write what's in r3 */
        l.ori r3, r0, SPI_SPSR_RX_CHECK /* r3 = , ensure loop just once */
        l.ori r3, r0, SPI_SPSR_RX_CHECK /* r3 = , ensure loop just once */
spi_xfer_poll:
spi_xfer_poll:
Line 155... Line 180...
        l.movhi r0, 0
        l.movhi r0, 0
        l.nop 0x1
        l.nop 0x1
        l.j 0
        l.j 0
        l.nop
        l.nop
        l.nop
        l.nop
 
 
 
 
 
 
#endif
#endif

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