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Line 40... |
#include "board.h"
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#include "board.h"
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#ifdef BOOTROM_SPI_FLASH
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#ifdef BOOTROM_SPI_FLASH
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/* Assembly program to go into the boot ROM */
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/* Assembly program to go into the boot ROM */
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/* For use with simple_spi SPI master core and standard SPI flash
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interface-compatible parts (ST M25P16 for example.)*/
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/* Currently just loads a program from SPI flash into RAM */
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/* Currently just loads a program from SPI flash into RAM */
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/* Assuming address at RAM_LOAD_BASE gets clobbered, we need
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/* Assuming address at RAM_LOAD_BASE gets clobbered, we need
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a byte writable address somewhere!*/
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a byte writable address somewhere!*/
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#define SPI_BASE SPI0_BASE
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#define SPI_BASE SPI0_BASE
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Line 71... |
spi_init:
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spi_init:
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l.ori r2, r0, SPI_SPCR_XFER_GO /* Setup SPCR with enable bit set */
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l.ori r2, r0, SPI_SPCR_XFER_GO /* Setup SPCR with enable bit set */
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l.sb SPI_SPCR(r4), r2
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l.sb SPI_SPCR(r4), r2
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l.sb SPI_SPSS(r4), r0 /* Clear SPI slave selects */
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l.sb SPI_SPSS(r4), r0 /* Clear SPI slave selects */
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l.ori r6, r0, SPI_SPSS_INIT
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l.ori r6, r0, SPI_SPSS_INIT
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l.sb SPI_SPSS(r4), r6 /* Now put in appropriate slave select */
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l.sb SPI_SPSS(r4), r6 /* Set appropriate slave select */
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l.jal spi_xfer
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l.jal spi_xfer
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l.ori r3, r0, 0x3 /* READ command opcode for SPI device */
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l.ori r3, r0, 0x3 /* READ command opcode for SPI device */
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l.jal spi_xfer
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l.jal spi_xfer
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#ifdef BOOTROM_ADDR_BYTE2
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l.ori r3, r0, BOOTROM_ADDR_BYTE2 /* Use addr if defined. MSB first */
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#else
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l.or r3, r0, r0
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l.or r3, r0, r0
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#endif
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l.jal spi_xfer
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l.jal spi_xfer
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#ifdef BOOTROM_ADDR_BYTE1
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l.ori r3, r0, BOOTROM_ADDR_BYTE1
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#else
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l.or r3, r0, r0
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l.or r3, r0, r0
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#endif
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l.jal spi_xfer
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l.jal spi_xfer
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#ifdef BOOTROM_ADDR_BYTE0
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l.ori r3, r0, BOOTROM_ADDR_BYTE0
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#else
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l.or r3, r0, r0
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l.or r3, r0, r0
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#endif
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l.movhi r6, 0
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l.movhi r6, 0
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l.movhi r7, 0xffff
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l.movhi r7, 0xffff
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copy:
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copy:
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l.jal spi_xfer /* Read a byte into r3 */
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l.jal spi_xfer /* Read a byte into r3 */
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l.add r8, r1, r6 /* Calculate store address */
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l.add r8, r1, r6 /* Calculate store address */
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l.sb 0(r8), r3 /* Write byte to memory */
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l.sb 0(r8), r3 /* Write byte to memory */
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l.addi r6, r6, 1 /* Increment counter */
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l.addi r6, r6, 1 /* Increment counter */
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l.sfeqi r6, 0x4 /* Is this the first word */
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l.sfeqi r6, 0x4 /* Is this the first word ?*/
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l.bf store_sizeword /* put sizeword in the register */
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l.bf store_sizeword /* put sizeword in the register */
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l.sfeq r6, r7 /* Check if we've finished loading the words */
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l.sfeq r6, r7 /* Check if we've finished loading the words */
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l.bnf copy /* Continue copying if not last word */
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l.bnf copy /* Continue copying if not last word */
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l.nop
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l.nop
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Line 112... |
l.ori r1, r1, RESET_ADDR
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l.ori r1, r1, RESET_ADDR
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l.jr r1
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l.jr r1
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l.sb SPI_SPSS(r4), r0 /* Clear SPI slave selects */
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l.sb SPI_SPSS(r4), r0 /* Clear SPI slave selects */
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store_sizeword:
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store_sizeword:
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#ifdef SPI_RETRY_IF_INSANE_SIZEWORD
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l.lwz r7, 0(r1) /* Size word is in first word of SDRAM */
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l.srli r10, r7, 16 /* Chop the sizeword we read in half */
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l.sfgtui r10, 0x0200 /* It's unlikely we'll ever load > 32MB */
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l.bf boot_init
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l.nop
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l.j copy
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l.nop
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#else
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l.j copy
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l.j copy
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l.lwz r7, 0(r1) /* Size word is in first word of SDRAM */
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l.lwz r7, 0(r1) /* Size word is in first word of SDRAM */
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#endif
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spi_xfer:
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spi_xfer:
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l.sb SPI_SPDR(r4), r3 /* Dummy write what's in r3 */
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l.sb SPI_SPDR(r4), r3 /* Dummy write what's in r3 */
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l.ori r3, r0, SPI_SPSR_RX_CHECK /* r3 = , ensure loop just once */
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l.ori r3, r0, SPI_SPSR_RX_CHECK /* r3 = , ensure loop just once */
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spi_xfer_poll:
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spi_xfer_poll:
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Line 180... |
l.movhi r0, 0
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l.movhi r0, 0
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l.nop 0x1
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l.nop 0x1
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l.j 0
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l.j 0
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l.nop
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l.nop
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l.nop
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l.nop
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#endif
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#endif
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