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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Ethernet MAC driver functions ////
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//// ////
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//// Description ////
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//// A collection of functions to help control the OpenCores ////
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//// 10/100 ethernet mac (ethmac) core. ////
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//// ////
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//// ////
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//// Author(s): ////
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//// - Julius Baxter, julius@opencores.org ////
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//// - Parts taken from Linux kernel's open_eth driver. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2009,2010 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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#ifndef _ETHMAC_H_
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#define _ETHMAC_H
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typedef unsigned int uint;
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/* Ethernet configuration registers */
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typedef struct _oeth_regs {
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uint moder; /* Mode Register */
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uint int_src; /* Interrupt Source Register */
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uint int_mask; /* Interrupt Mask Register */
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uint ipgt; /* Back to Bak Inter Packet Gap Register */
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uint ipgr1; /* Non Back to Back Inter Packet Gap Register 1 */
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uint ipgr2; /* Non Back to Back Inter Packet Gap Register 2 */
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uint packet_len; /* Packet Length Register (min. and max.) */
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uint collconf; /* Collision and Retry Configuration Register */
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uint tx_bd_num; /* Transmit Buffer Descriptor Number Register */
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uint ctrlmoder; /* Control Module Mode Register */
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uint miimoder; /* MII Mode Register */
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uint miicommand; /* MII Command Register */
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uint miiaddress; /* MII Address Register */
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uint miitx_data; /* MII Transmit Data Register */
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uint miirx_data; /* MII Receive Data Register */
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uint miistatus; /* MII Status Register */
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uint mac_addr0; /* MAC Individual Address Register 0 */
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uint mac_addr1; /* MAC Individual Address Register 1 */
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uint hash_addr0; /* Hash Register 0 */
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uint hash_addr1; /* Hash Register 1 */
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} oeth_regs;
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/* Ethernet buffer descriptor */
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typedef struct _oeth_bd {
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#if 0
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ushort len; /* Buffer length */
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ushort status; /* Buffer status */
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#else
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uint len_status;
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#endif
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uint addr; /* Buffer address */
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} oeth_bd;
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// From board.h
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#define ETH_BASE_ADD ETH0_BASE
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#define OETH_REG_BASE ETH_BASE_ADD
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#define OETH_BD_BASE (ETH_BASE_ADD + 0x400)
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#define OETH_TOTAL_BD 128
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#define OETH_MAXBUF_LEN 0x600
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/* Tx BD */
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#define OETH_TX_BD_READY 0x8000 /* Tx BD Ready */
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#define OETH_TX_BD_IRQ 0x4000 /* Tx BD IRQ Enable */
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#define OETH_TX_BD_WRAP 0x2000 /* Tx BD Wrap (last BD) */
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#define OETH_TX_BD_PAD 0x1000 /* Tx BD Pad Enable */
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#define OETH_TX_BD_CRC 0x0800 /* Tx BD CRC Enable */
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#define OETH_TX_BD_UNDERRUN 0x0100 /* Tx BD Underrun Status */
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#define OETH_TX_BD_RETRY 0x00F0 /* Tx BD Retry Status */
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#define OETH_TX_BD_RETLIM 0x0008 /* Tx BD Retransmission Limit Status */
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#define OETH_TX_BD_LATECOL 0x0004 /* Tx BD Late Collision Status */
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#define OETH_TX_BD_DEFER 0x0002 /* Tx BD Defer Status */
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#define OETH_TX_BD_CARRIER 0x0001 /* Tx BD Carrier Sense Lost Status */
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#define OETH_TX_BD_STATS (OETH_TX_BD_UNDERRUN | \
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OETH_TX_BD_RETRY | \
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OETH_TX_BD_RETLIM | \
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OETH_TX_BD_LATECOL | \
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OETH_TX_BD_DEFER | \
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OETH_TX_BD_CARRIER)
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/* Rx BD */
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#define OETH_RX_BD_EMPTY 0x8000 /* Rx BD Empty */
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#define OETH_RX_BD_IRQ 0x4000 /* Rx BD IRQ Enable */
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#define OETH_RX_BD_WRAP 0x2000 /* Rx BD Wrap (last BD) */
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#define OETH_RX_BD_MISS 0x0080 /* Rx BD Miss Status */
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#define OETH_RX_BD_OVERRUN 0x0040 /* Rx BD Overrun Status */
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#define OETH_RX_BD_INVSIMB 0x0020 /* Rx BD Invalid Symbol Status */
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#define OETH_RX_BD_DRIBBLE 0x0010 /* Rx BD Dribble Nibble Status */
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#define OETH_RX_BD_TOOLONG 0x0008 /* Rx BD Too Long Status */
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#define OETH_RX_BD_SHORT 0x0004 /* Rx BD Too Short Frame Status */
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#define OETH_RX_BD_CRCERR 0x0002 /* Rx BD CRC Error Status */
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#define OETH_RX_BD_LATECOL 0x0001 /* Rx BD Late Collision Status */
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#define OETH_RX_BD_STATS (OETH_RX_BD_MISS | \
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OETH_RX_BD_OVERRUN | \
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OETH_RX_BD_INVSIMB | \
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OETH_RX_BD_DRIBBLE | \
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OETH_RX_BD_TOOLONG | \
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OETH_RX_BD_SHORT | \
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OETH_RX_BD_CRCERR | \
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OETH_RX_BD_LATECOL)
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/* MODER Register */
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#define OETH_MODER_RXEN 0x00000001 /* Receive Enable */
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#define OETH_MODER_TXEN 0x00000002 /* Transmit Enable */
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#define OETH_MODER_NOPRE 0x00000004 /* No Preamble */
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#define OETH_MODER_BRO 0x00000008 /* Reject Broadcast */
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#define OETH_MODER_IAM 0x00000010 /* Use Individual Hash */
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#define OETH_MODER_PRO 0x00000020 /* Promiscuous (receive all) */
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#define OETH_MODER_IFG 0x00000040 /* Min. IFG not required */
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#define OETH_MODER_LOOPBCK 0x00000080 /* Loop Back */
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#define OETH_MODER_NOBCKOF 0x00000100 /* No Backoff */
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#define OETH_MODER_EXDFREN 0x00000200 /* Excess Defer */
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#define OETH_MODER_FULLD 0x00000400 /* Full Duplex */
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#define OETH_MODER_RST 0x00000800 /* Reset MAC */
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#define OETH_MODER_DLYCRCEN 0x00001000 /* Delayed CRC Enable */
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#define OETH_MODER_CRCEN 0x00002000 /* CRC Enable */
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#define OETH_MODER_HUGEN 0x00004000 /* Huge Enable */
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#define OETH_MODER_PAD 0x00008000 /* Pad Enable */
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#define OETH_MODER_RECSMALL 0x00010000 /* Receive Small */
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/* Interrupt Source Register */
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#define OETH_INT_TXB 0x00000001 /* Transmit Buffer IRQ */
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#define OETH_INT_TXE 0x00000002 /* Transmit Error IRQ */
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#define OETH_INT_RXF 0x00000004 /* Receive Frame IRQ */
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#define OETH_INT_RXE 0x00000008 /* Receive Error IRQ */
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#define OETH_INT_BUSY 0x00000010 /* Busy IRQ */
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#define OETH_INT_TXC 0x00000020 /* Transmit Control Frame IRQ */
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#define OETH_INT_RXC 0x00000040 /* Received Control Frame IRQ */
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/* Interrupt Mask Register */
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#define OETH_INT_MASK_TXB 0x00000001 /* Transmit Buffer IRQ Mask */
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#define OETH_INT_MASK_TXE 0x00000002 /* Transmit Error IRQ Mask */
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#define OETH_INT_MASK_RXF 0x00000004 /* Receive Frame IRQ Mask */
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#define OETH_INT_MASK_RXE 0x00000008 /* Receive Error IRQ Mask */
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#define OETH_INT_MASK_BUSY 0x00000010 /* Busy IRQ Mask */
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#define OETH_INT_MASK_TXC 0x00000020 /* Transmit Control Frame IRQ Mask */
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#define OETH_INT_MASK_RXC 0x00000040 /* Received Control Frame IRQ Mask */
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/* Control Module Mode Register */
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#define OETH_CTRLMODER_PASSALL 0x00000001 /* Pass Control Frames */
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#define OETH_CTRLMODER_RXFLOW 0x00000002 /* Receive Control Flow Enable */
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#define OETH_CTRLMODER_TXFLOW 0x00000004 /* Transmit Control Flow Enable */
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/* MII Mode Register */
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#define OETH_MIIMODER_CLKDIV 0x000000FF /* Clock Divider */
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#define OETH_MIIMODER_NOPRE 0x00000100 /* No Preamble */
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#define OETH_MIIMODER_RST 0x00000200 /* MIIM Reset */
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/* MII Command Register */
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#define OETH_MIICOMMAND_SCANSTAT 0x00000001 /* Scan Status */
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#define OETH_MIICOMMAND_RSTAT 0x00000002 /* Read Status */
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#define OETH_MIICOMMAND_WCTRLDATA 0x00000004 /* Write Control Data */
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/* MII Address Register */
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#define OETH_MIIADDRESS_FIAD 0x0000001F /* PHY Address */
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#define OETH_MIIADDRESS_RGAD 0x00001F00 /* RGAD Address */
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/* MII Status Register */
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#define OETH_MIISTATUS_LINKFAIL 0x00000001 /* Link Fail */
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#define OETH_MIISTATUS_BUSY 0x00000002 /* MII Busy */
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#define OETH_MIISTATUS_NVALID 0x00000004 /* Data in MII Status Register is invalid */
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/* Dummy function for now, just to make the driver compile */
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void ethmac_init();
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#endif
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