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https://opencores.org/ocsvn/openrisc/openrisc/trunk
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Rev 530 |
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Line 63... |
uint miistatus; /* MII Status Register */
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uint miistatus; /* MII Status Register */
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uint mac_addr0; /* MAC Individual Address Register 0 */
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uint mac_addr0; /* MAC Individual Address Register 0 */
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uint mac_addr1; /* MAC Individual Address Register 1 */
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uint mac_addr1; /* MAC Individual Address Register 1 */
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uint hash_addr0; /* Hash Register 0 */
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uint hash_addr0; /* Hash Register 0 */
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uint hash_addr1; /* Hash Register 1 */
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uint hash_addr1; /* Hash Register 1 */
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uint txctrl; /* Transmit control frame Register */
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uint rxctrl; /* Rx control frame Register */
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uint wbdbg; /* Wishbone state machine debug information */
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} oeth_regs;
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} oeth_regs;
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/* Ethernet buffer descriptor */
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/* Ethernet buffer descriptor */
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typedef struct _oeth_bd {
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typedef struct _oeth_bd {
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#if 0
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#if 0
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