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https://opencores.org/ocsvn/openrisc/openrisc/trunk
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Rev 488 |
Rev 489 |
Line 29... |
Line 29... |
l.nop
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l.nop
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/* =================================================== [ exceptions ] === */
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/* =================================================== [ exceptions ] === */
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.section .vectors, "ax"
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.section .vectors, "ax"
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/* ---[ 0x100: RESET exception ]----------------------------------------- */
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/* ---[ 0x100: RESET exception ]----------------------------------------- */
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.org 0x100
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.org 0x100
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l.movhi r0, 0
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l.movhi r0, 0
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l.movhi r1, 0
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l.movhi r1, 0
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l.movhi r2, 0
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l.movhi r2, 0
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Line 195... |
Line 194... |
/* ========================================================= [ entry ] === */
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/* ========================================================= [ entry ] === */
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.section .text
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.section .text
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ENTRY(_start)
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ENTRY(_start)
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/* Instruction cache enable */
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/* Instruction cache enable */
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/* Check if IC present and skip enabling otherwise */
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/* Check if IC present and skip enabling otherwise */
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l.mfspr r24,r0,SPR_UPR
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l.mfspr r24,r0,SPR_UPR
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l.andi r26,r24,SPR_UPR_ICP
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l.andi r26,r24,SPR_UPR_ICP
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l.sfeq r26,r0
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l.sfeq r26,r0
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