OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [drivers/] [or1200/] [include/] [spr-defs.h] - Diff between revs 393 and 535

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 393 Rev 535
Line 279... Line 279...
 */
 */
#define SPR_DTLBMR_V       0x00000001  /* Valid */
#define SPR_DTLBMR_V       0x00000001  /* Valid */
#define SPR_DTLBMR_PL1     0x00000002  /* Page Level 1 (if 0 then PL2) */
#define SPR_DTLBMR_PL1     0x00000002  /* Page Level 1 (if 0 then PL2) */
#define SPR_DTLBMR_CID     0x0000003c  /* Context ID */
#define SPR_DTLBMR_CID     0x0000003c  /* Context ID */
#define SPR_DTLBMR_LRU     0x000000c0  /* Least Recently Used */
#define SPR_DTLBMR_LRU     0x000000c0  /* Least Recently Used */
#define SPR_DTLBMR_VPN     0xfffff000  /* Virtual Page Number */
#define SPR_DTLBMR_VPN     0xffffe000  /* Virtual Page Number */
 
 
/*
/*
 * Bit definitions for the Data TLB Translate Register
 * Bit definitions for the Data TLB Translate Register
 *
 *
 */
 */
Line 295... Line 295...
#define SPR_DTLBTR_D       0x00000020  /* Dirty */
#define SPR_DTLBTR_D       0x00000020  /* Dirty */
#define SPR_DTLBTR_URE     0x00000040  /* User Read Enable */
#define SPR_DTLBTR_URE     0x00000040  /* User Read Enable */
#define SPR_DTLBTR_UWE     0x00000080  /* User Write Enable */
#define SPR_DTLBTR_UWE     0x00000080  /* User Write Enable */
#define SPR_DTLBTR_SRE     0x00000100  /* Supervisor Read Enable */
#define SPR_DTLBTR_SRE     0x00000100  /* Supervisor Read Enable */
#define SPR_DTLBTR_SWE     0x00000200  /* Supervisor Write Enable */
#define SPR_DTLBTR_SWE     0x00000200  /* Supervisor Write Enable */
#define SPR_DTLBTR_PPN     0xfffff000  /* Physical Page Number */
#define SPR_DTLBTR_PPN     0xffffe000  /* Physical Page Number */
 
 
#define DTLB_PR_NOLIMIT  ( SPR_DTLBTR_URE  | \
#define DTLB_PR_NOLIMIT  ( SPR_DTLBTR_URE  | \
                           SPR_DTLBTR_UWE  | \
                           SPR_DTLBTR_UWE  | \
                           SPR_DTLBTR_SRE  | \
                           SPR_DTLBTR_SRE  | \
                           SPR_DTLBTR_SWE  )
                           SPR_DTLBTR_SWE  )
Line 310... Line 310...
 */
 */
#define SPR_ITLBMR_V       0x00000001  /* Valid */
#define SPR_ITLBMR_V       0x00000001  /* Valid */
#define SPR_ITLBMR_PL1     0x00000002  /* Page Level 1 (if 0 then PL2) */
#define SPR_ITLBMR_PL1     0x00000002  /* Page Level 1 (if 0 then PL2) */
#define SPR_ITLBMR_CID     0x0000003c  /* Context ID */
#define SPR_ITLBMR_CID     0x0000003c  /* Context ID */
#define SPR_ITLBMR_LRU     0x000000c0  /* Least Recently Used */
#define SPR_ITLBMR_LRU     0x000000c0  /* Least Recently Used */
#define SPR_ITLBMR_VPN     0xfffff000  /* Virtual Page Number */
#define SPR_ITLBMR_VPN     0xffffe000  /* Virtual Page Number */
 
 
/*
/*
 * Bit definitions for the Instruction TLB Translate Register
 * Bit definitions for the Instruction TLB Translate Register
 *
 *
 */
 */
Line 324... Line 324...
#define SPR_ITLBTR_WOM     0x00000008  /* Weakly-Ordered Memory */
#define SPR_ITLBTR_WOM     0x00000008  /* Weakly-Ordered Memory */
#define SPR_ITLBTR_A       0x00000010  /* Accessed */
#define SPR_ITLBTR_A       0x00000010  /* Accessed */
#define SPR_ITLBTR_D       0x00000020  /* Dirty */
#define SPR_ITLBTR_D       0x00000020  /* Dirty */
#define SPR_ITLBTR_SXE     0x00000040  /* User Read Enable */
#define SPR_ITLBTR_SXE     0x00000040  /* User Read Enable */
#define SPR_ITLBTR_UXE     0x00000080  /* User Write Enable */
#define SPR_ITLBTR_UXE     0x00000080  /* User Write Enable */
#define SPR_ITLBTR_PPN     0xfffff000  /* Physical Page Number */
#define SPR_ITLBTR_PPN     0xffffe000  /* Physical Page Number */
 
 
#define ITLB_PR_NOLIMIT  ( SPR_ITLBTR_SXE  |    \
#define ITLB_PR_NOLIMIT  ( SPR_ITLBTR_SXE  |    \
                           SPR_ITLBTR_UXE  )
                           SPR_ITLBTR_UXE  )
 
 
/*
/*

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.