| Line 279... |
Line 279... |
*/
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*/
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#define SPR_DTLBMR_V 0x00000001 /* Valid */
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#define SPR_DTLBMR_V 0x00000001 /* Valid */
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#define SPR_DTLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */
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#define SPR_DTLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */
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#define SPR_DTLBMR_CID 0x0000003c /* Context ID */
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#define SPR_DTLBMR_CID 0x0000003c /* Context ID */
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#define SPR_DTLBMR_LRU 0x000000c0 /* Least Recently Used */
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#define SPR_DTLBMR_LRU 0x000000c0 /* Least Recently Used */
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#define SPR_DTLBMR_VPN 0xfffff000 /* Virtual Page Number */
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#define SPR_DTLBMR_VPN 0xffffe000 /* Virtual Page Number */
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|
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/*
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/*
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* Bit definitions for the Data TLB Translate Register
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* Bit definitions for the Data TLB Translate Register
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*
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*
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*/
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*/
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| Line 295... |
Line 295... |
#define SPR_DTLBTR_D 0x00000020 /* Dirty */
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#define SPR_DTLBTR_D 0x00000020 /* Dirty */
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#define SPR_DTLBTR_URE 0x00000040 /* User Read Enable */
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#define SPR_DTLBTR_URE 0x00000040 /* User Read Enable */
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#define SPR_DTLBTR_UWE 0x00000080 /* User Write Enable */
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#define SPR_DTLBTR_UWE 0x00000080 /* User Write Enable */
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#define SPR_DTLBTR_SRE 0x00000100 /* Supervisor Read Enable */
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#define SPR_DTLBTR_SRE 0x00000100 /* Supervisor Read Enable */
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#define SPR_DTLBTR_SWE 0x00000200 /* Supervisor Write Enable */
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#define SPR_DTLBTR_SWE 0x00000200 /* Supervisor Write Enable */
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#define SPR_DTLBTR_PPN 0xfffff000 /* Physical Page Number */
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#define SPR_DTLBTR_PPN 0xffffe000 /* Physical Page Number */
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|
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#define DTLB_PR_NOLIMIT ( SPR_DTLBTR_URE | \
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#define DTLB_PR_NOLIMIT ( SPR_DTLBTR_URE | \
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SPR_DTLBTR_UWE | \
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SPR_DTLBTR_UWE | \
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SPR_DTLBTR_SRE | \
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SPR_DTLBTR_SRE | \
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SPR_DTLBTR_SWE )
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SPR_DTLBTR_SWE )
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| Line 310... |
Line 310... |
*/
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*/
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#define SPR_ITLBMR_V 0x00000001 /* Valid */
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#define SPR_ITLBMR_V 0x00000001 /* Valid */
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#define SPR_ITLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */
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#define SPR_ITLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */
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#define SPR_ITLBMR_CID 0x0000003c /* Context ID */
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#define SPR_ITLBMR_CID 0x0000003c /* Context ID */
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#define SPR_ITLBMR_LRU 0x000000c0 /* Least Recently Used */
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#define SPR_ITLBMR_LRU 0x000000c0 /* Least Recently Used */
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#define SPR_ITLBMR_VPN 0xfffff000 /* Virtual Page Number */
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#define SPR_ITLBMR_VPN 0xffffe000 /* Virtual Page Number */
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|
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/*
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/*
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* Bit definitions for the Instruction TLB Translate Register
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* Bit definitions for the Instruction TLB Translate Register
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*
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*
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*/
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*/
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| Line 324... |
Line 324... |
#define SPR_ITLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */
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#define SPR_ITLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */
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#define SPR_ITLBTR_A 0x00000010 /* Accessed */
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#define SPR_ITLBTR_A 0x00000010 /* Accessed */
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#define SPR_ITLBTR_D 0x00000020 /* Dirty */
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#define SPR_ITLBTR_D 0x00000020 /* Dirty */
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#define SPR_ITLBTR_SXE 0x00000040 /* User Read Enable */
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#define SPR_ITLBTR_SXE 0x00000040 /* User Read Enable */
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#define SPR_ITLBTR_UXE 0x00000080 /* User Write Enable */
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#define SPR_ITLBTR_UXE 0x00000080 /* User Write Enable */
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#define SPR_ITLBTR_PPN 0xfffff000 /* Physical Page Number */
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#define SPR_ITLBTR_PPN 0xffffe000 /* Physical Page Number */
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|
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#define ITLB_PR_NOLIMIT ( SPR_ITLBTR_SXE | \
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#define ITLB_PR_NOLIMIT ( SPR_ITLBTR_SXE | \
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SPR_ITLBTR_UXE )
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SPR_ITLBTR_UXE )
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|
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/*
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/*
|
