URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
Rev 393 |
Rev 408 |
Line 36... |
Line 36... |
asm("l.add r3,r0,%0": : "r" (i));
|
asm("l.add r3,r0,%0": : "r" (i));
|
asm("l.nop %0": :"K" (NOP_EXIT));
|
asm("l.nop %0": :"K" (NOP_EXIT));
|
while (1);
|
while (1);
|
}
|
}
|
|
|
|
/* Enable user interrupts */
|
|
void
|
|
cpu_enable_user_interrupts(void)
|
|
{
|
|
/* Enable interrupts in supervisor register */
|
|
mtspr (SPR_SR, mfspr (SPR_SR) | SPR_SR_IEE);
|
|
}
|
|
|
/* Tick timer variable */
|
/* Tick timer variable */
|
unsigned long timer_ticks;
|
unsigned long timer_ticks;
|
|
|
/* Tick timer functions */
|
/* Tick timer functions */
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.