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URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [drivers/] [or1200/] [or1200-utils.c] - Diff between revs 408 and 411

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Rev 408 Rev 411
Line 1... Line 1...
#include "spr-defs.h"
#include "spr-defs.h"
#include "or1200-utils.h"
#include "or1200-utils.h"
#include "board.h" // For timer rate (IN_CLK, TICKS_PER_SEC)
#include "board.h" // For timer rate (IN_CLK, TICKS_PER_SEC)
 
 
/* For writing into SPR. */
/* For writing into SPR. */
void mtspr(unsigned long spr, unsigned long value)
void
 
mtspr(unsigned long spr, unsigned long value)
{
{
  asm("l.mtspr\t\t%0,%1,0": : "r" (spr), "r" (value));
  asm("l.mtspr\t\t%0,%1,0": : "r" (spr), "r" (value));
}
}
 
 
/* For reading SPR. */
/* For reading SPR. */
unsigned long mfspr(unsigned long spr)
unsigned long
 
mfspr(unsigned long spr)
{
{
  unsigned long value;
  unsigned long value;
  asm("l.mfspr\t\t%0,%1,0" : "=r" (value) : "r" (spr));
  asm("l.mfspr\t\t%0,%1,0" : "=r" (value) : "r" (spr));
  return value;
  return value;
}
}
 
 
/* Print out a character via simulator */
/* Print out a character via simulator */
void sim_putc(unsigned char c)
void
 
sim_putc(unsigned char c)
{
{
  asm("l.addi\tr3,%0,0": :"r" (c));
  asm("l.addi\tr3,%0,0": :"r" (c));
  asm("l.nop %0": :"K" (NOP_PUTC));
  asm("l.nop %0": :"K" (NOP_PUTC));
}
}
 
 
/* print long */
/* print long */
void report(unsigned long value)
void
 
report(unsigned long value)
{
{
  asm("l.addi\tr3,%0,0": :"r" (value));
  asm("l.addi\tr3,%0,0": :"r" (value));
  asm("l.nop %0": :"K" (NOP_REPORT));
  asm("l.nop %0": :"K" (NOP_REPORT));
}
}
 
 
/* Loops/exits simulation */
/* Loops/exits simulation */
void exit (int i)
void
 
exit (int i)
{
{
  asm("l.add r3,r0,%0": : "r" (i));
  asm("l.add r3,r0,%0": : "r" (i));
  asm("l.nop %0": :"K" (NOP_EXIT));
  asm("l.nop %0": :"K" (NOP_EXIT));
  while (1);
  while (1);
}
}
Line 49... Line 54...
/* Tick timer variable */
/* Tick timer variable */
unsigned long timer_ticks;
unsigned long timer_ticks;
 
 
/* Tick timer functions */
/* Tick timer functions */
/* Enable tick timer and interrupt generation */
/* Enable tick timer and interrupt generation */
void enable_timer(void)
void
 
cpu_enable_timer(void)
{
{
  mtspr(SPR_SR, SPR_SR_TEE | mfspr(SPR_SR));
 
  mtspr(SPR_TTMR, SPR_TTMR_IE | SPR_TTMR_RT | ((IN_CLK/TICKS_PER_SEC) & SPR_TTMR_PERIOD));
  mtspr(SPR_TTMR, SPR_TTMR_IE | SPR_TTMR_RT | ((IN_CLK/TICKS_PER_SEC) & SPR_TTMR_PERIOD));
 
  mtspr(SPR_SR, SPR_SR_TEE | mfspr(SPR_SR));
 
 
}
}
 
 
/* Disable tick timer and interrupt generation */
/* Disable tick timer and interrupt generation */
void disable_timer(void)
void
 
cpu_disable_timer(void)
{
{
  // Disable timer: clear it all!
  // Disable timer: clear it all!
  mtspr (SPR_SR, mfspr (SPR_SR) & ~SPR_SR_TEE);
  mtspr (SPR_SR, mfspr (SPR_SR) & ~SPR_SR_TEE);
  mtspr(SPR_TTMR, 0);
  mtspr(SPR_TTMR, 0);
 
 
}
}
 
 
/* Timer increment - called by interrupt routine */
/* Timer increment - called by interrupt routine */
void timer_tick(void)
/* Now actually done in interrupt vector code in crt0.S */
 
void
 
cpu_timer_tick(void)
{
{
  timer_ticks++;
  timer_ticks++;
  mtspr(SPR_TTMR, SPR_TTMR_IE | SPR_TTMR_RT | ((IN_CLK/TICKS_PER_SEC) & SPR_TTMR_PERIOD));
  mtspr(SPR_TTMR, SPR_TTMR_IE | SPR_TTMR_RT | ((IN_CLK/TICKS_PER_SEC) & SPR_TTMR_PERIOD));
}
}
 
 
/* Reset tick counter */
/* Reset tick counter */
void clear_timer_ticks(void)
void
 
cpu_reset_timer_ticks(void)
{
{
  timer_ticks=0;
  timer_ticks=0;
}
}
 
 
/* Get tick counter */
/* Get tick counter */
unsigned long get_timer_ticks(void)
unsigned long
 
cpu_get_timer_ticks(void)
{
{
  return timer_ticks;
  return timer_ticks;
}
}
 
 
/* Wait for 10ms */
/* Wait for 10ms */
void wait_10ms(void)
void
 
cpu_sleep_10ms(void)
{
{
  unsigned long first_time = get_timer_ticks();
  unsigned long first_time = cpu_get_timer_ticks();
  while (first_time == get_timer_ticks());
  while (first_time == cpu_get_timer_ticks());
}
}
 
 
 
 
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