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https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
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Rev 415 |
Line 77... |
Line 77... |
sper = (sper & ~SIMPLESPI_SPER_ICNT) | cnt;
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sper = (sper & ~SIMPLESPI_SPER_ICNT) | cnt;
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REG8((spi_base_adr[core] + SIMPLESPI_SPER)) = sper;
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REG8((spi_base_adr[core] + SIMPLESPI_SPER)) = sper;
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}
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}
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// slave_sel_dec is decoded (so asserted bit in right place)
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// No decode on slave select lines, so assert correct bit to select slave
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void
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void
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spi_core_slave_select(int core, char slave_sel_dec)
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spi_core_slave_select(int core, char slave_sel_dec)
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{
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{
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REG8((spi_base_adr[core] + SIMPLESPI_SSPU)) = slave_sel_dec;
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REG8((spi_base_adr[core] + SIMPLESPI_SSPU)) = slave_sel_dec;
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}
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}
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