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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Interrupt-driven Ethernet MAC test code ////
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//// ////
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//// Description ////
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//// Do ethernet receive path testing ////
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//// Relies on testbench to provide simulus - expects at least ////
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//// 256 packets to be sent. ////
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//// ////
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//// Author(s): ////
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//// - jb, jb@orsoc.se, with parts taken from Linux kernel ////
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//// open_eth driver. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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#include "cpu-utils.h"
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//#include "spr-defs.h"
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#include "board.h"
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#include "int.h"
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#include "uart.h"
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#include "ethmac.h"
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#include "printf.h"
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#include "eth-phy-mii.h"
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volatile unsigned tx_done;
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volatile unsigned rx_done;
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/* Functions in this file */
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void ethmac_setup(void);
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void ethphy_init(void);
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void oeth_dump_bds();
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/* Interrupt functions */
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void oeth_interrupt(void);
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static void oeth_rx(void);
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static void oeth_tx(void);
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/* Defining RTLSIM turns off use of real printf'ing to save time in simulation */
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#define RTLSIM
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#ifdef RTLSIM
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#define printk
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#else
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#define printk printf
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#endif
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/* Let the ethernet packets use a space beginning here for buffering */
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#define ETH_BUFF_BASE 0x01000000
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#define RXBUFF_PREALLOC 1
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#define TXBUFF_PREALLOC 1
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//#undef RXBUFF_PREALLOC
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//#undef TXBUFF_PREALLOC
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/* The transmitter timeout
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*/
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#define TX_TIMEOUT (2*HZ)
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/* Buffer number (must be 2^n)
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*/
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#define OETH_RXBD_NUM 16
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#define OETH_TXBD_NUM 16
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#define OETH_RXBD_NUM_MASK (OETH_RXBD_NUM-1)
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#define OETH_TXBD_NUM_MASK (OETH_TXBD_NUM-1)
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/* Buffer size
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*/
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#define OETH_RX_BUFF_SIZE 0x600
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#define OETH_TX_BUFF_SIZE 0x600
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/* Buffer size (if not XXBUF_PREALLOC
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*/
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#define MAX_FRAME_SIZE 1518
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/* The buffer descriptors track the ring buffers.
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*/
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struct oeth_private {
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//struct sk_buff* rx_skbuff[OETH_RXBD_NUM];
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//struct sk_buff* tx_skbuff[OETH_TXBD_NUM];
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unsigned short tx_next; /* Next buffer to be sent */
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unsigned short tx_last; /* Next buffer to be checked if packet sent */
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unsigned short tx_full; /* Buffer ring fuul indicator */
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unsigned short rx_cur; /* Next buffer to be checked if packet received */
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oeth_regs *regs; /* Address of controller registers. */
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oeth_bd *rx_bd_base; /* Address of Rx BDs. */
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oeth_bd *tx_bd_base; /* Address of Tx BDs. */
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// struct net_device_stats stats;
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};
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#define PHYNUM 7
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/* Scan the MIIM bus for PHYs */
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void scan_ethphys(void)
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{
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unsigned int phynum,regnum, i;
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volatile oeth_regs *regs;
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regs = (oeth_regs *)(OETH_REG_BASE);
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regs->miitx_data = 0;
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for(phynum=0;phynum<32;phynum++)
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{
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for (regnum=0;regnum<8;regnum++)
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{
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printk("scan_ethphys: phy %d r%d ",phynum, regnum);
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/* Now actually perform the read on the MIIM bus*/
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regs->miiaddress = (regnum << 8) | phynum; /* Basic Control Register */
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regs->miicommand = OETH_MIICOMMAND_RSTAT;
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while(!(regs->miistatus & OETH_MIISTATUS_BUSY)); /* Wait for command to be registered*/
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regs->miicommand = 0;
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while(regs->miistatus & OETH_MIISTATUS_BUSY);
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printk("%x\n",regs->miirx_data);
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}
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}
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}
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void ethmac_scanstatus(void)
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{
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volatile oeth_regs *regs;
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regs = (oeth_regs *)(OETH_REG_BASE);
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printk("Oeth: regs->miistatus %x regs->miirx_data %x\n",regs->miistatus, regs->miirx_data);
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regs->miiaddress = 0;
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regs->miitx_data = 0;
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regs->miicommand = OETH_MIICOMMAND_SCANSTAT;
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printk("Oeth: regs->miiaddress %x regs->miicommand %x\n",regs->miiaddress, regs->miicommand);
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//regs->miicommand = 0;
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volatile int i; for(i=0;i<1000;i++);
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while(regs->miistatus & OETH_MIISTATUS_BUSY) ;
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//spin_cursor();
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//printk("\r");
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//or32_exit(0);
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}
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void
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eth_mii_write(char phynum, short regnum, short data)
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{
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static volatile oeth_regs *regs = (oeth_regs *)(OETH_REG_BASE);
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regs->miiaddress = (regnum << 8) | phynum;
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regs->miitx_data = data;
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regs->miicommand = OETH_MIICOMMAND_WCTRLDATA;
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regs->miicommand = 0;
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while(regs->miistatus & OETH_MIISTATUS_BUSY);
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}
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short
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eth_mii_read(char phynum, short regnum)
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{
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static volatile oeth_regs *regs = (oeth_regs *)(OETH_REG_BASE);
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regs->miiaddress = (regnum << 8) | phynum;
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regs->miicommand = OETH_MIICOMMAND_RSTAT;
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regs->miicommand = 0;
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while(regs->miistatus & OETH_MIISTATUS_BUSY);
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return regs->miirx_data;
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}
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void ethphy_init(void)
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{
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/* Init the Alaska 88E1111 Phy */
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char alaska88e1111_ml501_phynum = 0x7;
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/* Init, reset */
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short ctl = eth_mii_read(alaska88e1111_ml501_phynum, MII_BMCR);
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ctl &= ~(BMCR_FULLDPLX|BMCR_SPEED100|BMCR_SPD2|BMCR_ANENABLE);
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ctl |= BMCR_SPEED100; // 100MBit
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ctl |= BMCR_FULLDPLX; // Full duplex
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eth_mii_write(alaska88e1111_ml501_phynum, MII_BMCR, ctl);
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// Setup Autoneg
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short adv = eth_mii_read(alaska88e1111_ml501_phynum, MII_ADVERTISE);
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adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_1000XFULL
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|ADVERTISE_1000XHALF | ADVERTISE_1000XPAUSE |
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ADVERTISE_1000XPSE_ASYM);
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adv |= ADVERTISE_10HALF;
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adv |= ADVERTISE_10FULL;
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adv |= ADVERTISE_100HALF;
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adv |= ADVERTISE_100FULL;
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eth_mii_write(alaska88e1111_ml501_phynum, MII_ADVERTISE, adv);
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// Disable gigabit???
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adv = eth_mii_read(alaska88e1111_ml501_phynum, MII_M1011_PHY_SPEC_CONTROL);
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adv &= ~(MII_1000BASETCONTROL_FULLDUPLEXCAP |
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MII_1000BASETCONTROL_HALFDUPLEXCAP);
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eth_mii_write(alaska88e1111_ml501_phynum, MII_M1011_PHY_SPEC_CONTROL, adv);
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// Even more disable gigabit?!
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adv = eth_mii_read(alaska88e1111_ml501_phynum, MII_CTRL1000);
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adv &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
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eth_mii_write(alaska88e1111_ml501_phynum, MII_CTRL1000, adv);
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// Restart autoneg
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printk("Resetting phy...\n");
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ctl = eth_mii_read(alaska88e1111_ml501_phynum, MII_BMCR);
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ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
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eth_mii_write(alaska88e1111_ml501_phynum, MII_BMCR, ctl);
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}
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void ethmac_setup(void)
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{
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// from arch/or32/drivers/open_eth.c
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volatile oeth_regs *regs;
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regs = (oeth_regs *)(OETH_REG_BASE);
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/* Reset MII mode module */
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regs->miimoder = OETH_MIIMODER_RST; /* MII Reset ON */
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regs->miimoder &= ~OETH_MIIMODER_RST; /* MII Reset OFF */
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regs->miimoder = 0x64; /* Clock divider for MII Management interface */
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/* Reset the controller.
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*/
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regs->moder = OETH_MODER_RST; /* Reset ON */
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regs->moder &= ~OETH_MODER_RST; /* Reset OFF */
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/* Setting TXBD base to OETH_TXBD_NUM.
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*/
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regs->tx_bd_num = OETH_TXBD_NUM;
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/* Set min/max packet length
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*/
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regs->packet_len = 0x00400600;
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/* Set IPGT register to recomended value
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*/
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regs->ipgt = 0x12;
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/* Set IPGR1 register to recomended value
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*/
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regs->ipgr1 = 0x0000000c;
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/* Set IPGR2 register to recomended value
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*/
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regs->ipgr2 = 0x00000012;
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/* Set COLLCONF register to recomended value
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*/
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regs->collconf = 0x000f003f;
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/* Set control module mode
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*/
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#if 0
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regs->ctrlmoder = OETH_CTRLMODER_TXFLOW | OETH_CTRLMODER_RXFLOW;
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#else
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regs->ctrlmoder = 0;
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#endif
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/* Clear MIIM registers */
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regs->miitx_data = 0;
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regs->miiaddress = 0;
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regs->miicommand = 0;
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regs->mac_addr1 = ETH_MACADDR0 << 8 | ETH_MACADDR1;
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regs->mac_addr0 = ETH_MACADDR2 << 24 | ETH_MACADDR3 << 16 | ETH_MACADDR4 << 8 | ETH_MACADDR5;
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/* Clear all pending interrupts
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*/
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regs->int_src = 0xffffffff;
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/* Promisc, IFG, CRCEn
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*/
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regs->moder |= OETH_MODER_PRO | OETH_MODER_PAD | OETH_MODER_IFG | OETH_MODER_CRCEN | OETH_MODER_FULLD;
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/* Enable interrupt sources.
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*/
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regs->int_mask = OETH_INT_MASK_TXB |
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OETH_INT_MASK_TXE |
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OETH_INT_MASK_RXF |
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OETH_INT_MASK_RXE |
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OETH_INT_MASK_BUSY |
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OETH_INT_MASK_TXC |
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OETH_INT_MASK_RXC;
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// Buffer setup stuff
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volatile oeth_bd *tx_bd, *rx_bd;
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int i,j,k;
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/* Initialize TXBD pointer
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*/
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tx_bd = (volatile oeth_bd *)OETH_BD_BASE;
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/* Initialize RXBD pointer
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*/
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rx_bd = ((volatile oeth_bd *)OETH_BD_BASE) + OETH_TXBD_NUM;
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/* Preallocated ethernet buffer setup */
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unsigned long mem_addr = ETH_BUFF_BASE; /* Defined at top */
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// Setup TX Buffers
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for(i = 0; i < OETH_TXBD_NUM; i++) {
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//tx_bd[i].len_status = OETH_TX_BD_PAD | OETH_TX_BD_CRC | OETH_RX_BD_IRQ;
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tx_bd[i].len_status = OETH_TX_BD_PAD | OETH_TX_BD_CRC;
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tx_bd[i].addr = mem_addr;
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mem_addr += OETH_TX_BUFF_SIZE;
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}
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tx_bd[OETH_TXBD_NUM - 1].len_status |= OETH_TX_BD_WRAP;
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// Setup RX buffers
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for(i = 0; i < OETH_RXBD_NUM; i++) {
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rx_bd[i].len_status = OETH_RX_BD_EMPTY | OETH_RX_BD_IRQ; // Init. with IRQ
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rx_bd[i].addr = mem_addr;
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mem_addr += OETH_RX_BUFF_SIZE;
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}
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rx_bd[OETH_RXBD_NUM - 1].len_status |= OETH_RX_BD_WRAP; // Last buffer wraps
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|
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/* Enable just the receiver
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*/
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regs->moder &= ~(OETH_MODER_RXEN | OETH_MODER_TXEN);
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regs->moder |= OETH_MODER_RXEN /* | OETH_MODER_TXEN*/;
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return;
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}
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|
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/* The interrupt handler.
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*/
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void
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oeth_interrupt(void)
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{
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|
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volatile oeth_regs *regs;
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regs = (oeth_regs *)(OETH_REG_BASE);
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|
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uint int_events;
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int serviced;
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serviced = 0;
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|
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/* Get the interrupt events that caused us to be here.
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*/
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int_events = regs->int_src;
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regs->int_src = int_events;
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|
|
|
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/* Handle receive event in its own function.
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*/
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if (int_events & (OETH_INT_RXF | OETH_INT_RXE)) {
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serviced |= 0x1;
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oeth_rx();
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}
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|
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/* Handle transmit event in its own function.
|
|
*/
|
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if (int_events & (OETH_INT_TXB | OETH_INT_TXE)) {
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serviced |= 0x2;
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oeth_tx();
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serviced |= 0x2;
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|
|
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}
|
|
|
|
/* Check for receive busy, i.e. packets coming but no place to
|
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* put them.
|
|
*/
|
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if (int_events & OETH_INT_BUSY) {
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serviced |= 0x4;
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if (!(int_events & (OETH_INT_RXF | OETH_INT_RXE)))
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oeth_rx();
|
|
}
|
|
|
|
return;
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
oeth_rx(void)
|
|
{
|
|
volatile oeth_regs *regs;
|
|
regs = (oeth_regs *)(OETH_REG_BASE);
|
|
|
|
volatile oeth_bd *rx_bdp;
|
|
int pkt_len, i;
|
|
int bad = 0;
|
|
|
|
rx_bdp = ((oeth_bd *)OETH_BD_BASE) + OETH_TXBD_NUM;
|
|
|
|
printk("r");
|
|
|
|
/* Find RX buffers marked as having received data */
|
|
for(i = 0; i < OETH_RXBD_NUM; i++)
|
|
{
|
|
bad=0;
|
|
if(!(rx_bdp[i].len_status & OETH_RX_BD_EMPTY)){ /* Looking for NOT empty buffers desc. */
|
|
/* Check status for errors.
|
|
*/
|
|
report(i);
|
|
report(rx_bdp[i].len_status);
|
|
if (rx_bdp[i].len_status & (OETH_RX_BD_TOOLONG | OETH_RX_BD_SHORT)) {
|
|
bad = 1;
|
|
report(0xbaad0001);
|
|
}
|
|
if (rx_bdp[i].len_status & OETH_RX_BD_DRIBBLE) {
|
|
bad = 1;
|
|
report(0xbaad0002);
|
|
}
|
|
if (rx_bdp[i].len_status & OETH_RX_BD_CRCERR) {
|
|
bad = 1;
|
|
report(0xbaad0003);
|
|
}
|
|
if (rx_bdp[i].len_status & OETH_RX_BD_OVERRUN) {
|
|
bad = 1;
|
|
report(0xbaad0004);
|
|
}
|
|
if (rx_bdp[i].len_status & OETH_RX_BD_MISS) {
|
|
report(0xbaad0005);
|
|
}
|
|
if (rx_bdp[i].len_status & OETH_RX_BD_LATECOL) {
|
|
bad = 1;
|
|
report(0xbaad0006);
|
|
}
|
|
if (bad) {
|
|
rx_bdp[i].len_status &= ~OETH_RX_BD_STATS;
|
|
rx_bdp[i].len_status |= OETH_RX_BD_EMPTY;
|
|
//exit(0xbaaaaaad);
|
|
|
|
continue;
|
|
}
|
|
else {
|
|
/*
|
|
Process the incoming frame.
|
|
*/
|
|
pkt_len = rx_bdp[i].len_status >> 16;
|
|
|
|
/* finish up */
|
|
rx_bdp[i].len_status &= ~OETH_RX_BD_STATS; /* Clear stats */
|
|
rx_bdp[i].len_status |= OETH_RX_BD_EMPTY; /* Mark RX BD as empty */
|
|
rx_done++;
|
|
report(rx_done);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
oeth_tx(void)
|
|
{
|
|
volatile oeth_bd *tx_bd;
|
|
int i;
|
|
|
|
tx_bd = (volatile oeth_bd *)OETH_BD_BASE; /* Search from beginning*/
|
|
|
|
/* Go through the TX buffs, search for one that was just sent */
|
|
for(i = 0; i < OETH_TXBD_NUM; i++)
|
|
{
|
|
/* Looking for buffer NOT ready for transmit. and IRQ enabled */
|
|
if( (!(tx_bd[i].len_status & (OETH_TX_BD_READY))) && (tx_bd[i].len_status & (OETH_TX_BD_IRQ)) )
|
|
{
|
|
/* Single threaded so no chance we have detected a buffer that has had its IRQ bit set but not its BD_READ flag. Maybe this won't work in linux */
|
|
tx_bd[i].len_status &= ~OETH_TX_BD_IRQ;
|
|
|
|
/* Probably good to check for TX errors here */
|
|
|
|
/* set our test variable */
|
|
tx_done = 1;
|
|
|
|
printk("T%d",i);
|
|
|
|
}
|
|
}
|
|
return;
|
|
}
|
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// Loop to check if a number is prime by doing mod divide of the number
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// to test by every number less than it
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int
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is_prime_number(unsigned long n)
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{
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unsigned long c;
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if (n < 2) return 0;
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for(c=2;c<n;c++)
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if ((n % c) == 0)
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return 0;
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return 1;
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}
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int main ()
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{
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/* Initialise handler vector */
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int_init();
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/* Install ethernet interrupt handler, it is enabled here too */
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int_add(ETH0_IRQ, oeth_interrupt, 0);
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/* Enable interrupts in supervisor register */
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cpu_enable_user_interrupts();
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rx_done = 0;
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ethmac_setup(); /* Configure MAC, TX/RX BDs and enable RX in MODER */
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#define NUM_PRIMES_TO_CHECK 1000
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char prime_check_results[NUM_PRIMES_TO_CHECK];
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unsigned long num_to_check;
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for(num_to_check=2;num_to_check<NUM_PRIMES_TO_CHECK;num_to_check++)
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{
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prime_check_results[num_to_check-2]
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= (char) is_prime_number(num_to_check);
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report(num_to_check | (0x1e<<24));
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report(prime_check_results[num_to_check-2] | (0x2e<<24));
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if (rx_done >= 255) // Check number of packets received, testbench
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// will hopefully send at least 256 packets
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exit(0x8000000d);
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}
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exit(0xbaaaaaad);
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}
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No newline at end of file
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No newline at end of file
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