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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Interrupt-driven Ethernet MAC transmit test code ////
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//// ////
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//// Description ////
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//// Transmits packets, testing both 100mbit and 10mbit modes. ////
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//// Expects testbench to be checking each packet sent. ////
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//// Define, ETH_TX_TEST_LENGTH, set further down, controls how ////
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//// many packets the test will send. ////
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//// ////
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//// Test data comes from pre-calculated array of random values, ////
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//// MAC TX buffer pointers are set to addresses in this array, ////
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//// saving copying the data around before transfers. ////
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//// ////
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//// Author(s): ////
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//// - jb, jb@orsoc.se, with parts taken from Linux kernel ////
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//// open_eth driver. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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#include "or32-utils.h"
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#include "spr-defs.h"
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#include "board.h"
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#include "int.h"
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#include "uart.h"
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#include "open-eth.h"
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#include "printf.h"
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#include "eth-phy-mii.h"
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volatile unsigned tx_done;
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volatile unsigned rx_done;
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static int next_tx_buf_num;
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/* Functions in this file */
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void ethmac_setup(void);
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/* Interrupt functions */
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void oeth_interrupt(void);
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static void oeth_rx(void);
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static void oeth_tx(void);
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/* Defining RTLSIM turns off use of real printf'ing to save time in simulation */
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#define RTLSIM
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#ifdef RTLSIM
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#define printk
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#else
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#define printk printf
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#endif
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/* Let the ethernet packets use a space beginning here for buffering */
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#define ETH_BUFF_BASE 0x01000000
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#define RXBUFF_PREALLOC 1
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#define TXBUFF_PREALLOC 1
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//#undef RXBUFF_PREALLOC
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//#undef TXBUFF_PREALLOC
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/* The transmitter timeout
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*/
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#define TX_TIMEOUT (2*HZ)
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/* Buffer number (must be 2^n)
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*/
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#define OETH_RXBD_NUM 16
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#define OETH_TXBD_NUM 16
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#define OETH_RXBD_NUM_MASK (OETH_RXBD_NUM-1)
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#define OETH_TXBD_NUM_MASK (OETH_TXBD_NUM-1)
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/* Buffer size
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*/
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#define OETH_RX_BUFF_SIZE 0x600 - 4
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#define OETH_TX_BUFF_SIZE 0x600 - 4
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/* OR32 Page size def */
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#define PAGE_SHIFT 13
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#define PAGE_SIZE (1UL << PAGE_SHIFT)
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/* How many buffers per page
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*/
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#define OETH_RX_BUFF_PPGAE (PAGE_SIZE/OETH_RX_BUFF_SIZE)
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#define OETH_TX_BUFF_PPGAE (PAGE_SIZE/OETH_TX_BUFF_SIZE)
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/* How many pages is needed for buffers
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*/
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#define OETH_RX_BUFF_PAGE_NUM (OETH_RXBD_NUM/OETH_RX_BUFF_PPGAE)
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#define OETH_TX_BUFF_PAGE_NUM (OETH_TXBD_NUM/OETH_TX_BUFF_PPGAE)
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/* Buffer size (if not XXBUF_PREALLOC
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*/
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#define MAX_FRAME_SIZE 1518
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/* The buffer descriptors track the ring buffers.
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*/
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struct oeth_private {
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//struct sk_buff* rx_skbuff[OETH_RXBD_NUM];
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//struct sk_buff* tx_skbuff[OETH_TXBD_NUM];
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unsigned short tx_next; /* Next buffer to be sent */
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unsigned short tx_last; /* Next buffer to be checked if packet sent */
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unsigned short tx_full; /* Buffer ring fuul indicator */
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unsigned short rx_cur; /* Next buffer to be checked if packet received */
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oeth_regs *regs; /* Address of controller registers. */
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oeth_bd *rx_bd_base; /* Address of Rx BDs. */
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oeth_bd *tx_bd_base; /* Address of Tx BDs. */
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// struct net_device_stats stats;
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};
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// Data array of data to transmit, tx_data_array[]
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#include "eth-rxtx-data.h"
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int tx_data_pointer;
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#define PHYNUM 7
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void
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eth_mii_write(char phynum, short regnum, short data)
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{
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static volatile oeth_regs *regs = (oeth_regs *)(OETH_REG_BASE);
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regs->miiaddress = (regnum << 8) | phynum;
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regs->miitx_data = data;
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regs->miicommand = OETH_MIICOMMAND_WCTRLDATA;
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regs->miicommand = 0;
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while(regs->miistatus & OETH_MIISTATUS_BUSY);
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}
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short
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eth_mii_read(char phynum, short regnum)
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{
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static volatile oeth_regs *regs = (oeth_regs *)(OETH_REG_BASE);
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regs->miiaddress = (regnum << 8) | phynum;
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regs->miicommand = OETH_MIICOMMAND_RSTAT;
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regs->miicommand = 0;
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while(regs->miistatus & OETH_MIISTATUS_BUSY);
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return regs->miirx_data;
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}
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// Wait here until all packets have been transmitted
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void wait_until_all_tx_clear(void)
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{
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int i;
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volatile oeth_bd *tx_bd;
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tx_bd = (volatile oeth_bd *)OETH_BD_BASE; /* Search from beginning*/
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int some_tx_waiting = 1;
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while (some_tx_waiting)
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{
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some_tx_waiting = 0;
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/* Go through the TX buffs, search for unused one */
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for(i = 0; i < OETH_TXBD_NUM; i++) {
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if((tx_bd[i].len_status & OETH_TX_BD_READY)) // Looking for buffer ready for transmit
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some_tx_waiting = 1;
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}
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}
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}
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void
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ethphy_set_10mbit(int phynum)
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{
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wait_until_all_tx_clear();
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// Hardset PHY to just use 10Mbit mode
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short cr = eth_mii_read(phynum, MII_BMCR);
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cr &= ~BMCR_ANENABLE; // Clear auto negotiate bit
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cr &= ~BMCR_SPEED100; // Clear fast eth. bit
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eth_mii_write(phynum, MII_BMCR, cr);
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}
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void
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ethphy_set_100mbit(int phynum)
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{
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wait_until_all_tx_clear();
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// Hardset PHY to just use 100Mbit mode
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short cr = eth_mii_read(phynum, MII_BMCR);
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cr |= BMCR_ANENABLE; // Clear auto negotiate bit
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cr |= BMCR_SPEED100; // Clear fast eth. bit
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eth_mii_write(phynum, MII_BMCR, cr);
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}
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void ethmac_setup(void)
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{
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// from arch/or32/drivers/open_eth.c
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volatile oeth_regs *regs;
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regs = (oeth_regs *)(OETH_REG_BASE);
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/* Reset MII mode module */
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regs->miimoder = OETH_MIIMODER_RST; /* MII Reset ON */
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regs->miimoder &= ~OETH_MIIMODER_RST; /* MII Reset OFF */
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regs->miimoder = 0x64; /* Clock divider for MII Management interface */
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/* Reset the controller.
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*/
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regs->moder = OETH_MODER_RST; /* Reset ON */
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regs->moder &= ~OETH_MODER_RST; /* Reset OFF */
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/* Setting TXBD base to OETH_TXBD_NUM.
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*/
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regs->tx_bd_num = OETH_TXBD_NUM;
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/* Set min/max packet length
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*/
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regs->packet_len = 0x00400600;
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/* Set IPGT register to recomended value
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*/
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regs->ipgt = 0x12;
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/* Set IPGR1 register to recomended value
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*/
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regs->ipgr1 = 0x0000000c;
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/* Set IPGR2 register to recomended value
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*/
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regs->ipgr2 = 0x00000012;
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/* Set COLLCONF register to recomended value
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*/
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regs->collconf = 0x000f003f;
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/* Set control module mode
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*/
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#if 0
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regs->ctrlmoder = OETH_CTRLMODER_TXFLOW | OETH_CTRLMODER_RXFLOW;
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#else
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regs->ctrlmoder = 0;
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#endif
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/* Clear MIIM registers */
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regs->miitx_data = 0;
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regs->miiaddress = 0;
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regs->miicommand = 0;
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regs->mac_addr1 = ETH_MACADDR0 << 8 | ETH_MACADDR1;
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regs->mac_addr0 = ETH_MACADDR2 << 24 | ETH_MACADDR3 << 16 | ETH_MACADDR4 << 8 | ETH_MACADDR5;
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/* Clear all pending interrupts
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*/
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regs->int_src = 0xffffffff;
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/* Promisc, IFG, CRCEn
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*/
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regs->moder |= OETH_MODER_PRO | OETH_MODER_PAD | OETH_MODER_IFG | OETH_MODER_CRCEN | OETH_MODER_FULLD;
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/* Enable interrupt sources.
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*/
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regs->int_mask = OETH_INT_MASK_TXB |
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OETH_INT_MASK_TXE |
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OETH_INT_MASK_RXF |
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OETH_INT_MASK_RXE |
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OETH_INT_MASK_BUSY |
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OETH_INT_MASK_TXC |
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OETH_INT_MASK_RXC;
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// Buffer setup stuff
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volatile oeth_bd *tx_bd, *rx_bd;
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int i,j,k;
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/* Initialize TXBD pointer
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*/
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tx_bd = (volatile oeth_bd *)OETH_BD_BASE;
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/* Initialize RXBD pointer
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*/
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rx_bd = ((volatile oeth_bd *)OETH_BD_BASE) + OETH_TXBD_NUM;
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/* Preallocated ethernet buffer setup */
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unsigned long mem_addr = ETH_BUFF_BASE; /* Defined at top */
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// Setup TX Buffers
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for(i = 0; i < OETH_TXBD_NUM; i++) {
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//tx_bd[i].len_status = OETH_TX_BD_PAD | OETH_TX_BD_CRC | OETH_RX_BD_IRQ;
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tx_bd[i].len_status = OETH_TX_BD_PAD | OETH_TX_BD_CRC;
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tx_bd[i].addr = mem_addr;
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mem_addr += OETH_TX_BUFF_SIZE;
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}
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tx_bd[OETH_TXBD_NUM - 1].len_status |= OETH_TX_BD_WRAP;
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// Setup RX buffers
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for(i = 0; i < OETH_RXBD_NUM; i++) {
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rx_bd[i].len_status = OETH_RX_BD_EMPTY | OETH_RX_BD_IRQ; // Init. with IRQ
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rx_bd[i].addr = mem_addr;
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mem_addr += OETH_RX_BUFF_SIZE;
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}
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rx_bd[OETH_RXBD_NUM - 1].len_status |= OETH_RX_BD_WRAP; // Last buffer wraps
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/* Enable JUST the transmiter
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*/
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regs->moder &= ~(OETH_MODER_RXEN | OETH_MODER_TXEN);
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regs->moder |= /*OETH_MODER_RXEN |*/ OETH_MODER_TXEN;
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next_tx_buf_num = 0; // init tx buffer pointer
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return;
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}
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/* Setup buffer descriptors with data */
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/* length is in BYTES */
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void tx_packet(void* data, int length)
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{
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volatile oeth_regs *regs;
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regs = (oeth_regs *)(OETH_REG_BASE);
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volatile oeth_bd *tx_bd;
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volatile int i;
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tx_bd = (volatile oeth_bd *)OETH_BD_BASE;
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tx_bd = (struct oeth_bd*) &tx_bd[next_tx_buf_num];
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// If it's in use - wait
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while ((tx_bd->len_status & OETH_TX_BD_IRQ));
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/* Clear all of the status flags.
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*/
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tx_bd->len_status &= ~OETH_TX_BD_STATS;
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/* If the frame is short, tell CPM to pad it.
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*/
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#define ETH_ZLEN 60 /* Min. octets in frame sans FCS */
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if (length <= ETH_ZLEN)
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tx_bd->len_status |= OETH_TX_BD_PAD;
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else
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tx_bd->len_status &= ~OETH_TX_BD_PAD;
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#ifdef _ETH_RXTX_DATA_H_
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// Set the address pointer to the place
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// in memory where the data is and transmit from there
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tx_bd->addr = (char*) &tx_data_array[tx_data_pointer&~(0x3)];
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tx_data_pointer += length;
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if (tx_data_pointer > (255*1024))
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tx_data_pointer = 0;
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#else
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if (data){
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//Copy the data into the transmit buffer, byte at a time
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char* data_p = (char*) data;
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char* data_b = (char*) tx_bd->addr;
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for(i=0;i<length;i++)
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{
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data_b[i] = data_p[i];
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}
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}
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#endif
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/* Set the length of the packet's data in the buffer descriptor */
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tx_bd->len_status = (tx_bd->len_status & 0x0000ffff) |
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((length&0xffff) << 16);
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|
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/* Send it on its way. Tell controller its ready, interrupt when sent
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* and to put the CRC on the end.
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*/
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tx_bd->len_status |= (OETH_TX_BD_READY | OETH_TX_BD_CRC | OETH_TX_BD_IRQ);
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next_tx_buf_num = (next_tx_buf_num + 1) & OETH_TXBD_NUM_MASK;
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return;
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}
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/* enable RX, loop waiting for arrived packets and print them out */
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void oeth_monitor_rx(void)
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{
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volatile oeth_regs *regs;
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regs = (oeth_regs *)(OETH_REG_BASE);
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/* Set RXEN in MAC MODER */
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regs->moder = OETH_MODER_RXEN | regs->moder;
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volatile oeth_bd *rx_bd;
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rx_bd = ((volatile oeth_bd *)OETH_BD_BASE) + OETH_TXBD_NUM;
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volatile int i;
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while (1)
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{
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for(i=0;i<OETH_RXBD_NUM;i++)
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{
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if (!(rx_bd[i].len_status & OETH_RX_BD_EMPTY)) /* Not empty */
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{
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// Something in this buffer!
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printk("Oeth: RX in buf %d - len_status: 0x%lx\n",i, rx_bd[i].len_status);
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/* Clear recieved bit */
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rx_bd[i].len_status |= OETH_RX_BD_EMPTY;
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printk("\t end of packet\n\n");
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}
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}
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}
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}
|
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|
|
|
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char broadcast_ping_packet[] = {
|
|
0xff,0xff,0xff,0xff,0xff,0xff, /*SRC MAC*/
|
|
0x00, 0x12, 0x34, 0x56, 0x78, 0x9a, /*SRC MAC*/
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0x08,0x00,
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0x45,
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0x00,
|
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0x00,0x54,
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0x00,0x00,
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0x40,
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0x00,
|
|
0x40,
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|
0x01,
|
|
0xef,0xef,
|
|
0xc0,0xa8,0x64,0x58, /* Source IP */
|
|
0xc0,0xa8,0x64,0xff, /* Dest. IP */
|
|
/* ICMP Message body */
|
|
0x08,0x00,0x7d,0x65,0xa7,0x20,0x00,0x01,0x68,0x25,0xa5,0x4a,0xcf,0x05,0x0c,0x00,0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x18,0x19,0x1a,0x1b,0x1c,0x1d,0x1e,0x1f,0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,0x30,0x31,0x32,0x33,0x34,0x35,0x36,0x37};
|
|
|
|
|
|
char big_broadcast_ping_packet[] = {
|
|
0xff,0xff,0xff,0xff,0xff,0xff, /*SRC MAC*/
|
|
0x00, 0x12, 0x34, 0x56, 0x78, 0x9a, /*SRC MAC*/
|
|
0x08,0x00,
|
|
0x45,
|
|
0x00,
|
|
// 0x00,0x54, /* length */
|
|
0x05,0x1c, /* length */
|
|
0x00,0x00,
|
|
0x40,
|
|
0x00,
|
|
0x40,
|
|
0x01,
|
|
0xee,0xf5,
|
|
0xc0,0xa8,0x64,0x9b, /* Source IP */
|
|
0xc0,0xa8,0x64,0xff, /* Dest. IP */
|
|
/* ICMP Message body */
|
|
0x08,0x00,0x7d,0x65,0xa7,0x20,0x00,0x01,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,
|
|
15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,
|
|
40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,
|
|
65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,
|
|
90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,
|
|
111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,
|
|
130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,
|
|
149,150,151,152,153,154,155,156,157,158,159,160,161,162,163,164,165,166,167,
|
|
168,169,170,171,172,173,174,175,176,177,178,179,180,181,182,183,184,185,186,
|
|
187,188,189,190,191,192,193,194,195,196,197,198,199,200,201,202,203,204,205,
|
|
206,207,208,209,210,211,212,213,214,215,216,217,218,219,220,221,222,223,224,
|
|
225,226,227,228,229,230,231,232,233,234,235,236,237,238,239,240,241,242,243,
|
|
244,245,246,247,248,249,250,251,252,253,254,255,
|
|
0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,
|
|
15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,
|
|
40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,
|
|
65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,
|
|
90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,
|
|
111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,
|
|
130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,
|
|
149,150,151,152,153,154,155,156,157,158,159,160,161,162,163,164,165,166,167,
|
|
168,169,170,171,172,173,174,175,176,177,178,179,180,181,182,183,184,185,186,
|
|
187,188,189,190,191,192,193,194,195,196,197,198,199,200,201,202,203,204,205,
|
|
206,207,208,209,210,211,212,213,214,215,216,217,218,219,220,221,222,223,224,
|
|
225,226,227,228,229,230,231,232,233,234,235,236,237,238,239,240,241,242,243,
|
|
244,245,246,247,248,249,250,251,252,253,254,255,
|
|
0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,
|
|
15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,
|
|
40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,
|
|
65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,
|
|
90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,
|
|
111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,
|
|
130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,
|
|
149,150,151,152,153,154,155,156,157,158,159,160,161,162,163,164,165,166,167,
|
|
168,169,170,171,172,173,174,175,176,177,178,179,180,181,182,183,184,185,186,
|
|
187,188,189,190,191,192,193,194,195,196,197,198,199,200,201,202,203,204,205,
|
|
206,207,208,209,210,211,212,213,214,215,216,217,218,219,220,221,222,223,224,
|
|
225,226,227,228,229,230,231,232,233,234,235,236,237,238,239,240,241,242,243,
|
|
244,245,246,247,248,249,250,251,252,253,254,255,
|
|
0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,
|
|
15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,
|
|
40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,
|
|
65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,
|
|
90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,
|
|
111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,
|
|
130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,
|
|
149,150,151,152,153,154,155,156,157,158,159,160,161,162,163,164,165,166,167,
|
|
168,169,170,171,172,173,174,175,176,177,178,179,180,181,182,183,184,185,186,
|
|
187,188,189,190,191,192,193,194,195,196,197,198,199,200,201,202,203,204,205,
|
|
206,207,208,209,210,211,212,213,214,215,216,217,218,219,220,221,222,223,224,
|
|
225,226,227,228,229,230,231,232,233,234,235,236,237,238,239,240,241,242,243,
|
|
244,245,246,247,248,249,250,251,252,253,254,255,
|
|
0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,
|
|
15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,
|
|
40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,
|
|
65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,
|
|
90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,
|
|
111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,
|
|
130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,
|
|
149,150,151,152,153,154,155,156,157,158,159,160,161,162,163,164,165,166,167,
|
|
168,169,170,171,172,173,174,175,176,177,178,179,180,181,182,183,184,185,186,
|
|
187,188,189,190,191,192,193,194,195,196,197,198,199,200,201,202,203,204,205,
|
|
206,207,208,209,210,211,212,213,214,215,216,217,218,219,220,221,222,223,224,
|
|
225,226,227,228,229,230,231,232,233,234,235,236,237,238,239,240,241,242,243,
|
|
244,245,246,247,248,249,250,251,252,253,254,255};
|
|
|
|
|
|
/* This should be 98 bytes big */
|
|
char ping_packet[] = {
|
|
0x00, 0x24, 0xe8, 0x91, 0x7c, 0x0d, /*DST MAC*/
|
|
//0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /*DST MAC*/
|
|
0x00, 0x12, 0x34, 0x56, 0x78, 0x9a, /*SRC MAC*/
|
|
0x08, 0x00, /*TYPE*/
|
|
/* IP */
|
|
0x45, /* Version, header length*/
|
|
0x00, /* Differentiated services field */
|
|
0x00, 0x54, /* Total length */
|
|
0x00, 0x00, /* Identification */
|
|
0x40, /* Flags */
|
|
0x00, /* Fragment offset */
|
|
0x40, /* Time to live */
|
|
0x01, /* Protocol (0x01 = ICMP */
|
|
0xef, 0xf3, /* Header checksum */
|
|
//0xc0, 0xa8, 0x64, 0xDE, /* Source IP */
|
|
0xc0, 0xa8, 0x0, 0x58, /* Source IP */
|
|
//0xa, 0x1, 0x1, 0x3, /* Source IP */
|
|
0xc0, 0xa8, 0x64, 0x69, /* Dest. IP */
|
|
0xc0, 0xa8, 0x0, 0xb, /* Dest. IP */
|
|
//0xa, 0x1, 0x1, 0x1, /* Dest. IP */
|
|
/* ICMP Message body */
|
|
0x08, 0x00, 0x9a, 0xd4, 0xc8, 0x18, 0x00, 0x01, 0xd9, 0x8c, 0x54,
|
|
0x4a, 0x7b, 0x37, 0x01, 0x00, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d,
|
|
0x0e, 0x0f, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18,
|
|
0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, 0x20, 0x21, 0x22, 0x23,
|
|
0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e,
|
|
0x2f, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37
|
|
};
|
|
|
|
|
|
/* The interrupt handler.
|
|
*/
|
|
void
|
|
oeth_interrupt(void)
|
|
{
|
|
|
|
volatile oeth_regs *regs;
|
|
regs = (oeth_regs *)(OETH_REG_BASE);
|
|
|
|
uint int_events;
|
|
int serviced;
|
|
|
|
serviced = 0;
|
|
|
|
/* Get the interrupt events that caused us to be here.
|
|
*/
|
|
int_events = regs->int_src;
|
|
regs->int_src = int_events;
|
|
|
|
|
|
#ifndef RTLSIM
|
|
printk(".");
|
|
|
|
printk("\n=tx_ | %x | %x | %x | %x | %x | %x | %x | %x\n",
|
|
((oeth_bd *)(OETH_BD_BASE))->len_status,
|
|
((oeth_bd *)(OETH_BD_BASE+8))->len_status,
|
|
((oeth_bd *)(OETH_BD_BASE+16))->len_status,
|
|
((oeth_bd *)(OETH_BD_BASE+24))->len_status,
|
|
((oeth_bd *)(OETH_BD_BASE+32))->len_status,
|
|
((oeth_bd *)(OETH_BD_BASE+40))->len_status,
|
|
((oeth_bd *)(OETH_BD_BASE+48))->len_status,
|
|
((oeth_bd *)(OETH_BD_BASE+56))->len_status);
|
|
|
|
printk("=rx_ | %x | %x | %x | %x | %x | %x | %x | %x\n",
|
|
((oeth_bd *)(OETH_BD_BASE+64))->len_status,
|
|
((oeth_bd *)(OETH_BD_BASE+64+8))->len_status,
|
|
((oeth_bd *)(OETH_BD_BASE+64+16))->len_status,
|
|
((oeth_bd *)(OETH_BD_BASE+64+24))->len_status,
|
|
((oeth_bd *)(OETH_BD_BASE+64+32))->len_status,
|
|
((oeth_bd *)(OETH_BD_BASE+64+40))->len_status,
|
|
((oeth_bd *)(OETH_BD_BASE+64+48))->len_status,
|
|
((oeth_bd *)(OETH_BD_BASE+64+56))->len_status);
|
|
|
|
printk("=int | txb %d | txe %d | rxb %d | rxe %d | busy %d\n",
|
|
(int_events & OETH_INT_TXB) > 0,
|
|
(int_events & OETH_INT_TXE) > 0,
|
|
(int_events & OETH_INT_RXF) > 0,
|
|
(int_events & OETH_INT_RXE) > 0,
|
|
(int_events & OETH_INT_BUSY) > 0);
|
|
#endif
|
|
|
|
|
|
|
|
/* Handle receive event in its own function.
|
|
*/
|
|
if (int_events & (OETH_INT_RXF | OETH_INT_RXE)) {
|
|
serviced |= 0x1;
|
|
oeth_rx();
|
|
}
|
|
|
|
/* Handle transmit event in its own function.
|
|
*/
|
|
if (int_events & (OETH_INT_TXB | OETH_INT_TXE)) {
|
|
serviced |= 0x2;
|
|
oeth_tx();
|
|
serviced |= 0x2;
|
|
|
|
}
|
|
|
|
/* Check for receive busy, i.e. packets coming but no place to
|
|
* put them.
|
|
*/
|
|
if (int_events & OETH_INT_BUSY) {
|
|
serviced |= 0x4;
|
|
#ifndef RTLSIM
|
|
printk("b");
|
|
#endif
|
|
if (!(int_events & (OETH_INT_RXF | OETH_INT_RXE)))
|
|
oeth_rx();
|
|
}
|
|
|
|
|
|
#if 0
|
|
if (serviced == 0) {
|
|
void die(const char * str, struct pt_regs * regs, long err);
|
|
int show_stack(unsigned long *esp);
|
|
printk("!");
|
|
// printk("unserviced irq\n");
|
|
// show_stack(NULL);
|
|
// die("unserviced irq\n", regs, 801);
|
|
}
|
|
#endif
|
|
|
|
if (serviced == 0)
|
|
printk("\neth interrupt called but nothing serviced\n");
|
|
|
|
else /* Something happened ... either RX or TX */
|
|
printk(" | serviced 0x%x\n", serviced);
|
|
|
|
return;
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
oeth_rx(void)
|
|
{
|
|
volatile oeth_regs *regs;
|
|
regs = (oeth_regs *)(OETH_REG_BASE);
|
|
|
|
volatile oeth_bd *rx_bdp;
|
|
int pkt_len, i;
|
|
int bad = 0;
|
|
|
|
rx_bdp = ((oeth_bd *)OETH_BD_BASE) + OETH_TXBD_NUM;
|
|
|
|
printk("r");
|
|
|
|
|
|
/* Find RX buffers marked as having received data */
|
|
for(i = 0; i < OETH_RXBD_NUM; i++)
|
|
{
|
|
bad=0;
|
|
if(!(rx_bdp[i].len_status & OETH_RX_BD_EMPTY)){ /* Looking for NOT empty buffers desc. */
|
|
/* Check status for errors.
|
|
*/
|
|
if (rx_bdp[i].len_status & (OETH_RX_BD_TOOLONG | OETH_RX_BD_SHORT)) {
|
|
bad = 1;
|
|
report(0xbaad0001);
|
|
}
|
|
if (rx_bdp[i].len_status & OETH_RX_BD_DRIBBLE) {
|
|
bad = 1;
|
|
report(0xbaad0002);
|
|
}
|
|
if (rx_bdp[i].len_status & OETH_RX_BD_CRCERR) {
|
|
bad = 1;
|
|
report(0xbaad0003);
|
|
}
|
|
if (rx_bdp[i].len_status & OETH_RX_BD_OVERRUN) {
|
|
bad = 1;
|
|
report(0xbaad0004);
|
|
}
|
|
if (rx_bdp[i].len_status & OETH_RX_BD_MISS) {
|
|
report(0xbaad0005);
|
|
}
|
|
if (rx_bdp[i].len_status & OETH_RX_BD_LATECOL) {
|
|
bad = 1;
|
|
report(0xbaad0006);
|
|
}
|
|
if (bad) {
|
|
rx_bdp[i].len_status &= ~OETH_RX_BD_STATS;
|
|
rx_bdp[i].len_status |= OETH_RX_BD_EMPTY;
|
|
exit(0xbaaaaaad);
|
|
|
|
continue;
|
|
}
|
|
else {
|
|
/* Process the incoming frame.
|
|
*/
|
|
pkt_len = rx_bdp[i].len_status >> 16;
|
|
|
|
/* Do something here with the data - copy it into userspace, perhaps*/
|
|
printk("\t end of packet\n\n");
|
|
|
|
|
|
/* finish up */
|
|
rx_bdp[i].len_status &= ~OETH_RX_BD_STATS; /* Clear stats */
|
|
rx_bdp[i].len_status |= OETH_RX_BD_EMPTY; /* Mark RX BD as empty */
|
|
rx_done++;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
oeth_tx(void)
|
|
{
|
|
volatile oeth_bd *tx_bd;
|
|
int i;
|
|
|
|
tx_bd = (volatile oeth_bd *)OETH_BD_BASE; /* Search from beginning*/
|
|
|
|
/* Go through the TX buffs, search for one that was just sent */
|
|
for(i = 0; i < OETH_TXBD_NUM; i++)
|
|
{
|
|
/* Looking for buffer NOT ready for transmit. and IRQ enabled */
|
|
if( (!(tx_bd[i].len_status & (OETH_TX_BD_READY))) && (tx_bd[i].len_status & (OETH_TX_BD_IRQ)) )
|
|
{
|
|
/* Single threaded so no chance we have detected a buffer that has had its IRQ bit set but not its BD_READ flag. Maybe this won't work in linux */
|
|
tx_bd[i].len_status &= ~OETH_TX_BD_IRQ;
|
|
|
|
/* Probably good to check for TX errors here */
|
|
|
|
/* set our test variable */
|
|
tx_done++;
|
|
|
|
printk("T%d",i);
|
|
|
|
}
|
|
}
|
|
return;
|
|
}
|
|
|
|
// A function and defines to fill and transmit a packet
|
|
#define MAX_TX_BUFFER 1532
|
|
static char tx_buffer[MAX_TX_BUFFER];
|
|
static unsigned long tx_data = 0x2ef2e242;
|
|
static inline char gen_next_tx_byte(void)
|
|
{
|
|
// Bit of LFSR action
|
|
tx_data = ((~(((((tx_data&(1<<25))>>25)^((tx_data&(1<<13))>>13))^((tx_data&(1<<2))>>2)))&0x01) | (tx_data<<1));
|
|
//tx_data++;
|
|
return (char) tx_data & 0xff;
|
|
}
|
|
|
|
void
|
|
fill_and_tx_packet(int size)
|
|
{
|
|
int i;
|
|
char tx_byte;
|
|
|
|
|
|
volatile oeth_regs *regs;
|
|
regs = (oeth_regs *)(OETH_REG_BASE);
|
|
|
|
volatile oeth_bd *tx_bd;
|
|
|
|
tx_bd = (volatile oeth_bd *)OETH_BD_BASE;
|
|
tx_bd = (struct oeth_bd*) &tx_bd[next_tx_buf_num];
|
|
|
|
|
|
// If it's in use - wait
|
|
while ((tx_bd->len_status & OETH_TX_BD_IRQ));
|
|
|
|
#ifndef _ETH_RXTX_DATA_H_
|
|
/* Copy the data into the transmit buffer, byte at a time */
|
|
char* data_b = (char*) tx_bd->addr;
|
|
for(i=0;i<size;i++)
|
|
{
|
|
data_b[i] = gen_next_tx_byte();
|
|
}
|
|
#endif
|
|
|
|
tx_packet((void*)0, size);
|
|
}
|
|
|
|
//#define WAIT_PACKET_TX(x) while(tx_done<x)
|
|
#define WAIT_PACKET_TX(x)
|
|
|
|
int main ()
|
|
{
|
|
tx_data_pointer = 0;
|
|
|
|
/* Initialise handler vector */
|
|
int_init();
|
|
|
|
/* Install ethernet interrupt handler, it is enabled here too */
|
|
int_add(ETH0_IRQ, oeth_interrupt, 0);
|
|
|
|
/* Enable interrupts in supervisor register */
|
|
mtspr (SPR_SR, mfspr (SPR_SR) | SPR_SR_IEE);
|
|
|
|
ethmac_setup(); /* Configure MAC, TX/RX BDs and enable RX and TX in MODER */
|
|
|
|
/* clear tx_done, the tx interrupt handler will set it when it's been transmitted */
|
|
tx_done = 0;
|
|
rx_done = 0;
|
|
|
|
int i;
|
|
ethphy_set_100mbit(0);
|
|
|
|
#ifndef ETH_TX_TEST_LENGTH
|
|
# define ETH_TX_TEST_LENGTH 128
|
|
//# define ETH_TX_TEST_LENGTH OETH_TX_BUFF_SIZE
|
|
#endif
|
|
|
|
for(i=5;i<ETH_TX_TEST_LENGTH;i+=1)
|
|
fill_and_tx_packet(i);
|
|
|
|
ethphy_set_10mbit(0);
|
|
for(i=5;i<ETH_TX_TEST_LENGTH;i+=1)
|
|
fill_and_tx_packet(i);
|
|
|
|
exit(0x8000000d);
|
|
|
|
|
|
}
|
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No newline at end of file
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No newline at end of file
|