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Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [tests/] [or1200/] [sim/] [or1200-basic.S] - Diff between revs 425 and 530

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Rev 425 Rev 530
Line 81... Line 81...
 
 
/* =================================================== [ start ] === */
/* =================================================== [ start ] === */
 
 
        .global _start
        .global _start
_start:
_start:
 
        l.jal _cache_init
        /* Instruction cache enable */
 
        /* Check if IC present and skip enabling otherwise */
 
        l.mfspr r24,r0,SPR_UPR
 
        l.andi  r26,r24,SPR_UPR_ICP
 
        l.sfeq  r26,r0
 
        l.bf    .L8
 
        l.nop
 
 
 
        /* Disable IC */
 
        l.mfspr r6,r0,SPR_SR
 
        l.addi  r5,r0,-1
 
        l.xori  r5,r5,SPR_SR_ICE
 
        l.and   r5,r6,r5
 
        l.mtspr r0,r5,SPR_SR
 
 
 
        /* Establish cache block size
 
        If BS=0, 16;
 
        If BS=1, 32;
 
        r14 contain block size
 
        */
 
        l.mfspr r24,r0,SPR_ICCFGR
 
        l.andi  r26,r24,SPR_ICCFGR_CBS
 
        l.srli  r28,r26,7
 
        l.ori   r30,r0,16
 
        l.sll   r14,r30,r28
 
 
 
        /* Establish number of cache sets
 
        r16 contains number of cache sets
 
        r28 contains log(# of cache sets)
 
        */
 
        l.andi  r26,r24,SPR_ICCFGR_NCS
 
        l.srli  r28,r26,3
 
        l.ori   r30,r0,1
 
        l.sll   r16,r30,r28
 
 
 
        /* Invalidate IC */
 
        l.addi  r6,r0,0
 
        l.sll   r5,r14,r28
 
 
 
.L7:
 
        l.mtspr r0,r6,SPR_ICBIR
 
        l.sfne  r6,r5
 
        l.bf    .L7
 
        l.add   r6,r6,r14
 
 
 
        /* Enable IC */
 
        l.mfspr r6,r0,SPR_SR
 
        l.ori   r6,r6,SPR_SR_ICE
 
        l.mtspr r0,r6,SPR_SR
 
        l.nop
 
        l.nop
 
        l.nop
 
        l.nop
 
        l.nop
 
        l.nop
 
        l.nop
 
        l.nop
        l.nop
 
 
.L8:
 
        /* Data cache enable */
 
        /* Check if DC present and skip enabling otherwise */
 
        l.mfspr r24,r0,SPR_UPR
 
        l.andi  r26,r24,SPR_UPR_DCP
 
        l.sfeq  r26,r0
 
        l.bf    .L10
 
        l.nop
 
        /* Disable DC */
 
        l.mfspr r6,r0,SPR_SR
 
        l.addi  r5,r0,-1
 
        l.xori  r5,r5,SPR_SR_DCE
 
        l.and   r5,r6,r5
 
        l.mtspr r0,r5,SPR_SR
 
        /* Establish cache block size
 
           If BS=0, 16;
 
           If BS=1, 32;
 
           r14 contain block size
 
        */
 
        l.mfspr r24,r0,SPR_DCCFGR
 
        l.andi  r26,r24,SPR_DCCFGR_CBS
 
        l.srli  r28,r26,7
 
        l.ori   r30,r0,16
 
        l.sll   r14,r30,r28
 
        /* Establish number of cache sets
 
           r16 contains number of cache sets
 
           r28 contains log(# of cache sets)
 
        */
 
        l.andi  r26,r24,SPR_DCCFGR_NCS
 
        l.srli  r28,r26,3
 
        l.ori   r30,r0,1
 
        l.sll   r16,r30,r28
 
        /* Invalidate DC */
 
        l.addi  r6,r0,0
 
        l.sll   r5,r14,r28
 
.L9:
 
        l.mtspr r0,r6,SPR_DCBIR
 
        l.sfne  r6,r5
 
        l.bf    .L9
 
        l.add   r6,r6,r14
 
        /* Enable DC */
 
        l.mfspr r6,r0,SPR_SR
 
        l.ori   r6,r6,SPR_SR_DCE
 
        l.mtspr r0,r6,SPR_SR
 
.L10:
 
        // Kick off test
        // Kick off test
        l.jal   _main
        l.jal   _main
        l.nop
        l.nop
 
 
 
 
Line 1098... Line 997...
        l.ori   r4, r4, 0xdea0
        l.ori   r4, r4, 0xdea0
        l.sub   r3, r3, r4 /* Should now be 0x8000000d */
        l.sub   r3, r3, r4 /* Should now be 0x8000000d */
        l.nop   0x2
        l.nop   0x2
        l.ori   r3, r0, 0 /* Clear R3 */
        l.ori   r3, r0, 0 /* Clear R3 */
        l.nop   0x1 /* Exit simulation */
        l.nop   0x1 /* Exit simulation */
 
        l.nop
 
        l.nop

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