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https://opencores.org/ocsvn/openrisc/openrisc/trunk
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| Rev 502 |
Rev 530 |
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Line 100... |
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/* =================================================== [ start ] === */
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/* =================================================== [ start ] === */
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.global _start
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.global _start
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_start:
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_start:
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// Clear all regs
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// Clear regs
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l.movhi r1, 0
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l.movhi r1, 0
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l.movhi r2, 0
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l.movhi r2, 0
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l.movhi r3, 0
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l.movhi r3, 0
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l.movhi r4, 0
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l.movhi r4, 0
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l.movhi r5, 0
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l.movhi r5, 0
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l.movhi r6, 0
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l.movhi r6, 0
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l.movhi r7, 0
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l.movhi r8, 0
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l.movhi r9, 0
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l.movhi r10, 0
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l.movhi r11, 0
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l.movhi r12, 0
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l.movhi r13, 0
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l.movhi r14, 0
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l.movhi r15, 0
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l.movhi r16, 0
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l.movhi r17, 0
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l.movhi r18, 0
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l.movhi r19, 0
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l.movhi r20, 0
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l.movhi r21, 0
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l.movhi r22, 0
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l.movhi r23, 0
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l.movhi r24, 0
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l.movhi r25, 0
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l.movhi r26, 0
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l.movhi r27, 0
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l.movhi r28, 0
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l.movhi r29, 0
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l.movhi r30, 0
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l.movhi r31, 0
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#ifdef OR1200_IMPL_CY
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#ifdef OR1200_IMPL_CY
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// Kick off test
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// Kick off test
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l.jal _main
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l.jal _main
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#else
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#else
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| Line 147... |
Line 122... |
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/* =================================================== [ main ] === */
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/* =================================================== [ main ] === */
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#define CHECK_CY_CLEAR \
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#define CHECK_CY_CLEAR \
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l.mfspr r20, r0, SPR_SR ; \
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l.mfspr r6, r0, SPR_SR ; \
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l.andi r21, r20, SPR_SR_CY ; \
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l.andi r6, r6, SPR_SR_CY ; \
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l.sfne r21, r0 ; \
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l.sfne r6, r0 ; \
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l.bf _fail ; \
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l.bf _fail ; \
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l.nop
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l.nop
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#define CHECK_CY_SET \
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#define CHECK_CY_SET \
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l.mfspr r20, r0, SPR_SR ; \
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l.mfspr r6, r0, SPR_SR ; \
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l.andi r21, r20, SPR_SR_CY ; \
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l.andi r6, r6, SPR_SR_CY ; \
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l.sfnei r21, SPR_SR_CY ; \
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l.sfnei r6, SPR_SR_CY ; \
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l.bf _fail ; \
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l.bf _fail ; \
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l.nop
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l.nop
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.global _main
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.global _main
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_main:
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_main:
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