| Line 146... |
Line 146... |
l.sw -20(r1),r8
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l.sw -20(r1),r8
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l.mfspr r2, r0, SPR_EEAR_BASE
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l.mfspr r2, r0, SPR_EEAR_BASE
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/* Find the entry/set for this address */
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/* Find the entry/set for this address */
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l.srli r13, r2, 13 /* r13 = VPN, shift by size 8192 = 2**13 */
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l.srli r13, r2, 13 /* r13 = VPN, shift by size 8192 = 2**13 */
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l.andi r4, r13, 0x3f /* 64 entries = 6 bit mask, r4 = set number */
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l.andi r4, r13, 0x3f /* 64 entries = 6 bit mask, r4 = set number */
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/* If page is in the 0xc0000000 space we map to 16MB part of
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/* If page is in the 0xc0000000 space we map to 4MB part of
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memory, ie 0x0 => 0x01000000, otherwise 1-1 mapping */
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memory, ie 0x0 => 0x00400000, otherwise 1-1 mapping */
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l.movhi r5, hi(0xc0000000)
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l.movhi r5, hi(0xc0000000)
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l.ori r5, r5, lo(0xc0000000)
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l.ori r5, r5, lo(0xc0000000)
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l.srli r5, r5, 13 /* Get page address, shift by page size, 13 bits */
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l.srli r5, r5, 13 /* Get page address, shift by page size, 13 bits */
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l.movhi r6, hi(0xff << 11) /* Mask for top byte of VPN */
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l.movhi r6, hi(0xff << 11) /* Mask for top byte of VPN */
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l.ori r6, r6, lo(0xff << 11)
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l.ori r6, r6, lo(0xff << 11)
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| Line 178... |
Line 178... |
l.mtspr r4, r7, SPR_DTLBTR_BASE(0) /* Write to DTLTR register */
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l.mtspr r4, r7, SPR_DTLBTR_BASE(0) /* Write to DTLTR register */
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l.j _dtlb_done
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l.j _dtlb_done
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l.addi r14, r14, 1 /* Incremement low-mapping counter */
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l.addi r14, r14, 1 /* Incremement low-mapping counter */
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|
|
_highmem_map:
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_highmem_map:
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/* Do top byte, 0xc0->0x01, mapping for this request */
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/* Do top byte, 0xc00->0x004, mapping for this request */
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/* Setup value for translate register */
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/* Setup value for translate register */
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l.movhi r6, hi(SPR_ITLBTR_PPN) /* PPN mask into r6 */
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l.movhi r6, hi(SPR_ITLBTR_PPN) /* PPN mask into r6 */
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l.ori r6, r6, lo(SPR_ITLBTR_PPN)
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l.ori r6, r6, lo(SPR_ITLBTR_PPN)
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l.and r7, r2, r6 /* AND address with PPN mask */
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l.and r7, r2, r6 /* AND address with PPN mask */
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l.movhi r8, hi(0xff000000) /* Top byte address mask */
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l.movhi r8, hi(0xffff0000) /* Top byte address mask */
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l.or r7, r8, r7 /* Set top byte to 0xff */
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l.or r7, r8, r7 /* Set top byte to 0xff */
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l.xor r7, r8, r7 /* Now clear top byte with XOR */
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l.xor r7, r8, r7 /* Now clear top byte with XOR */
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l.movhi r8, hi(0x01000000) /* Top address byte */
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l.movhi r8, hi(0x00400000) /* Top address byte */
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l.or r7, r8, r7 /* Set top address byte */
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l.or r7, r8, r7 /* Set top address byte */
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l.ori r7, r7, DTLB_PR_NOLIMIT /* Set all execute enables, no lims. */
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l.ori r7, r7, DTLB_PR_NOLIMIT /* Set all execute enables, no lims. */
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l.mtspr r4, r7, SPR_DTLBTR_BASE(0) /* Write to DTLTR register */
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l.mtspr r4, r7, SPR_DTLBTR_BASE(0) /* Write to DTLTR register */
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l.addi r15, r15, 1 /* Incremement low-mapping counter */
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l.addi r15, r15, 1 /* Incremement low-mapping counter */
|
|
|
| Line 573... |
Line 573... |
l.movhi r4, hi(_dmmu_invalidate)
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l.movhi r4, hi(_dmmu_invalidate)
|
l.ori r4, r4, lo(_dmmu_invalidate)
|
l.ori r4, r4, lo(_dmmu_invalidate)
|
l.jalr r4
|
l.jalr r4
|
l.ori r3, r0, 64 /* Put number of entries in r3 */
|
l.ori r3, r0, 64 /* Put number of entries in r3 */
|
|
|
l.movhi r5, hi(0x01000000)
|
l.movhi r5, hi(0x00400000)
|
/* Write a word to the place where we'll translate to */
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/* Write a word to the place where we'll translate to */
|
l.movhi r7, hi(0xaabbccdd)
|
l.movhi r7, hi(0xaabbccdd)
|
l.ori r7, r7, lo(0xaabbccdd)
|
l.ori r7, r7, lo(0xaabbccdd)
|
l.sw 0(r5), r7 /* Shouldn't trigger MMU */
|
l.sw 0(r5), r7 /* Shouldn't trigger MMU */
|
l.sfne r14, r0
|
l.sfne r14, r0
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| Line 591... |
Line 591... |
l.movhi r4, hi(lo_dmmu_en)
|
l.movhi r4, hi(lo_dmmu_en)
|
l.ori r4, r4, lo(lo_dmmu_en)
|
l.ori r4, r4, lo(lo_dmmu_en)
|
l.jalr r4
|
l.jalr r4
|
l.nop
|
l.nop
|
|
|
/* Now start test. 0xc0000000 should go to 0x01000000 */
|
/* Now start test. 0xc0000000 should go to 0x00400000 */
|
l.lwz r8, 0(r5) /* Should cause DMMU miss, lomem */
|
l.lwz r8, 0(r5) /* Should cause DMMU miss, lomem */
|
/* Check value was OK */
|
/* Check value was OK */
|
l.sfne r7, r8
|
l.sfne r7, r8
|
l.bf _dmmu_test_error
|
l.bf _dmmu_test_error
|
l.nop
|
l.nop
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| Line 618... |
Line 618... |
l.nop
|
l.nop
|
l.sfnei r15, 0x1 /* hi-mem counter should still be 0 */
|
l.sfnei r15, 0x1 /* hi-mem counter should still be 0 */
|
l.bf _dmmu_test_error
|
l.bf _dmmu_test_error
|
l.nop
|
l.nop
|
|
|
/* Now start test. 0xc0000000 should go to 0x01000000 */
|
/* Now start test. 0xc0000000 should go to 0x00400000 */
|
l.lwz r8, 0(r5) /* Should cause DMMU miss, lomem */
|
l.lwz r8, 0(r5) /* Should cause DMMU miss, lomem */
|
/* Check value was OK */
|
/* Check value was OK */
|
l.sfne r7, r8
|
l.sfne r7, r8
|
l.bf _dmmu_test_error
|
l.bf _dmmu_test_error
|
l.nop
|
l.nop
|
